R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1253

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Table 26.3 Boundary Scan Instructions
26.4.2
JTBPR is a 1-bit register and is connected between the TDI and TDO pins when JTIR is set to
BYPASS mode. JTBPR cannot be read from or written to by the CPU.
26.4.3
JTBSR is a shift register to control the external input and output pins of this LSI and is distributed
across the pads. The initial values are undefined. JTBSR cannot be accessed by the CPU. The
EXTEST, SAMPLE/PRELOAD, CLAMP, and HIGHZ instructions are issued to apply JTBSR in
boundary-scan testing conformant to the JTAG standard.
Table 26.4 shows the correspondence between the JTBSR bits and the pins of this LSI.
TS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bypass Register (JTBPR)
Boundary Scan Register (JTBSR)
TS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Instruction
EXTEST
IDCODE (initial value)
CLAMP
HIGHZ
SAMPLE/PRELOAD
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BYPASS
Rev. 2.00 Oct. 21, 2009 Page 1219 of 1454
Section 26 Boundary Scan
REJ09B0498-0200

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