R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 377

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.12
In this LSI, idle cycles can be inserted between the consecutive external accesses. By inserting the
idle cycle, data conflicts between ROM read cycle whose output floating time is long and an
access cycle from/to high-speed memory or I/O interface can be prevented.
9.12.1
When this LSI consecutively accesses external address space, it can insert an idle cycle between
bus cycles in the following four cases. These conditions are determined by the sequence of read
and write and previously accessed area.
1. When read cycles of different areas in the external address space occur consecutively
2. When an external write cycle occurs immediately after an external read cycle
3. When an external read cycle occurs immediately after an external write cycle
4. When an external access occurs immediately after a DMAC or EXDMAC single address
Up to four idle cycles can be inserted under the conditions shown above. The number of idle
cycles to be inserted should be specified to prevent data conflicts between the output data from a
previously accessed device and data from a subsequently accessed device.
Under conditions 1 and 2, which are the conditions to insert idle cycles after read, the number of
idle cycles can be selected from setting A specified by bits IDLCA1 and IDLCA0 in IDLCR or
setting B specified by bits IDLCB1 and IDLCB0 in IDLCR: Setting A can be selected from one to
four cycles, and setting B can be selected from one or two to four cycles. Setting A or B can be
specified for each area by setting bits IDLSEL7 to IDLSEL0 in IDLCR. Note that bits IDLSEL7
to IDLSEL0 correspond to the previously accessed area of the consecutive accesses.
The number of idle cycles to be inserted under conditions 3 and 4, which are conditions to insert
idle cycles after write, can be determined by setting A as described above.
After the reset release, IDLCR is initialized to four idle cycle insertion under all conditions 1 to 4
shown above.
Table 9.28 shows the correspondence between conditions 1 to 4 and number of idle cycles to be
inserted for each area. Table 9.29 shows the correspondence between the number of idle cycles to
be inserted specified by settings A and B, and number of cycles to be inserted.
transfer (write cycle)
Idle Cycle
Operation
Rev. 2.00 Oct. 21, 2009 Page 343 of 1454
Section 9 Bus Controller (BSC)
REJ09B0498-0200