R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 229
R5F61665N50FPV
Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61665N50FPV.pdf
(1492 pages)
Specifications of R5F61665N50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
IDLS0
IDLCB1
IDLCB0
IDLCA1
IDLCA0
IDLSEL7
IDLSEL6
IDLSEL5
IDLSEL4
IDLSEL3
IDLSEL2
IDLSEL1
IDLSEL0
Initial
Value
1
1
1
1
1
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Idle Cycle Insertion 0
Inserts an idle cycle between the bus cycles when the
external read cycle is followed by external write cycle.
0: No idle cycle is inserted
1: An idle cycle is inserted
Idle Cycle State Number Select B
Specifies the number of idle cycles to be inserted for
the idle condition specified by IDLS1 and IDLS0.
00: No idle cycle is inserted
01: 2 idle cycles are inserted
00: 3 idle cycles are inserted
01: 4 idle cycles are inserted
Idle Cycle State Number Select A
Specifies the number of idle cycles to be inserted for
the idle condition specified by IDLS3 to IDLS0.
00: 1 idle cycle is inserted
01: 2 idle cycles are inserted
10: 3 idle cycles are inserted
11: 4 idle cycles are inserted
Idle Cycle Number Select
Specifies the number of idle cycles to be inserted for
each area for the idle insertion condition specified by
IDLS1 and IDLS0.
0: Number of idle cycles to be inserted for area n is
1: Number of idle cycles to be inserted for area n is
(n = 7 to 0)
specified by IDLCA1 and IDLCA0.
specified by IDLCB1 and IDLCB0.
Rev. 2.00 Oct. 21, 2009 Page 195 of 1454
Section 9 Bus Controller (BSC)
REJ09B0498-0200
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