R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1104

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 22 A/D Converter
22.3.3
ADCSR controls A/D conversion operations.
Bit
7
6
5
Rev. 2.00 Oct. 21, 2009 Page 1070 of 1454
REJ09B0498-0200
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written to this bit, to clear the flag.
Bit Name
ADF
ADIE
ADST
A/D Control/Status Register 1 (ADCSR_1) for Unit 1
R/(W)*
ADF
7
0
Initial
Value
0
0
0
ADIE
R/W
R/W
R/(W)* A/D End Flag
R/W
R/W
6
0
Description
A status flag that indicates the end of A/D conversion.
[Setting conditions]
[Clearing conditions]
A/D Interrupt Enable
Setting this bit to 1 enables ADI interrupts by ADF.
A/D Start
Clearing this bit to 0 stops A/D conversion, and the A/D
converter enters wait state.
Setting this bit to 1 starts A/D conversion. In single mode, this bit
is cleared to 0 automatically when A/D conversion on the
specified channel ends. In scan mode, A/D conversion
continues sequentially on the specified channels until this bit is
cleared to 0 by software, a reset, or hardware standby mode. In
addition, when the ADSTCLR bit in ADCR is 1, the ADST bit is
automatically cleared to 0 upon completion of A/D conversion for
all of the selected channels to stop A/D conversion.
The ADST bit is automatically cleared at a different time from
that of setting the ADF bit. The ADST bit is cleared before
setting the ADF bit.
ADST
R/W
5
0
Completion of A/D conversion in single mode
Completion of A/D conversion on all specified channels in
scan mode
Writing of 0 after reading ADF = 1
(When the CPU is used to clear this flag by writing 0 while
the corresponding interrupt is enabled, be sure to read the
flag after writing 0 to it.)
Reading from ADDR after activation of the DMAC or DTC by
an ADI interrupt
EXCKS
R/W
4
0
CH3
R/W
3
0
CH2
R/W
2
0
CH1
R/W
1
0
CH0
R/W
0
0

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