R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 328

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Bus Controller (BSC)
9.10.12 Refresh Control
This LSI includes a DRAM refresh control function. The refresh method is the CAS before RAS
(CBR) refresh. Self-refresh cycles can be performed in software standby mode.
The refresh control function is enabled when area 2 is specified as the DRAM space by the
DRAME and DTYPE bits in DRAMCR.
(1)
Set the RFSHE bit in REFCR to 1 to select the CBR refresh mode.
A CBR refresh cycle is performed when the value set in RTCOR matches the RTCNT value
(compare match). RTCNT is an up-counter operated on the input clock specified by bits RTCK2
to RTCK0 in REFCR. RTCNT is initialized upon the compare match and restarts to count up with
H'00. Accordingly, a CBR refresh cycle is repeated at intervals specified by bits RTCK2 to
RTCK0 in RTCOR. Set the bits so that the required refresh intervals of the DRAM must be
satisfied.
Since setting bits RTCK2 to RTCK0 starts RTCNT to count up, set RTCNT and RTCOR before
setting bits RTCK2 to RTCK0. When changing RTCNT and RTCOR, the counting operation
should be halted. When changing bits RTCK2 to RTCK0, change them only after disabling
external access and bus release by the EXDMAC, and if the write data buffer function is in use,
disabling the write data buffer function and reading the external space.
The external space cannot be accessed in CBR refresh mode.
Figure 9.52 shows RTCNT operation, figure 9.53 shows compare match timing, and figure 9.54
shows CBR refresh timing. Table 9.23 lists the pin states during a CBR refresh cycle.
Rev. 2.00 Oct. 21, 2009 Page 294 of 1454
REJ09B0498-0200
CAS before RAS (CBR) Refresh Mode
RTCOR
H'00
Refresh request
RTCNT
Figure 9.52 RTCNT Operation

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