R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1313

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

28.8.4
When the IOKEEP bit is 0, Bφ/SDRAMφ output is undefined for a maximum of one cycle
immediately after exit from deep software standby mode. At this time, the output state cannot be
guaranteed. Even when the IOKEEP bit is set to 1, Bφ/SDRAMφ output is undefined for a
maximum of one cycle immediately after the IOKEEP bit is cleared to 0 after deep software
standby mode was canceled, and the output state cannot be guaranteed
However, clock can be normally output by canceling deep software standby mode with the
IOKEEP bit set to 1 and then controlling the Bφ/SDRAMφ οutput with the IOKEEP and PSTOP1
bits. Following procedure takes Bφ for example. (See figure 28.3)
1. Change the value of the PSTOP1 bit from 0 to 1 to fix the Bφ output at the high level (given
2. Clear the IOKEEP bit to 0 to end retention of the Bφ state.
3. Clear the PSTOP1 bit to 0 to enable Bφ output.
In case of the SDRAMφ, clock can be normally output by controlling the PSTOP0 bit instead of
the PSTOP1 bit in the same way as the procedure above mentioned. For the port state when the
IOKEEP bit is set to 1, see section 28.8.3, Pin State on Exit from Deep Software Standby Mode.
that the Bφ output was already fixed high).
(1) B φ output cannot be guaranteed.
(2) The procedure to guarantee B φ output is used.
Bφ/SDRAMφ Operation after Exit from Deep Software Standby Mode
Figure 28.3 Bφ Operation after Exit from Deep Software Standby Mode
Oscillator
NMI
Internal reset
Iφ
Bφ
Bφ
When IOKEEP = 0
When IOKEEP = 1
(IOKEEP=1)
Deep software standby mode
Clock is undefined
When IOKEEP = 1, the clock can be normally output
by using the PSTOP1 bit.
Rev. 2.00 Oct. 21, 2009 Page 1279 of 1454
PSTOP1
set
IOKEEP
IOKEEP
cleared
cleared
Section 28 Power-Down Modes
PSTOP1
cleared
REJ09B0498-0200