R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 443

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3)
A transfer is started by a transfer request signal (DREQ) from an external device. When a DMA
transfer is enabled (DTE = 1), the DMA transfer is started by the DREQ assertion. When a DMA
transfer between on-chip peripheral modules is performed, select an activation source from the
auto request and on-chip module interrupt (the external request cannot be used).
A transfer request signal is input to the DREQ pin. The DREQ signal is detected on the falling
edge or low level. Whether the falling edge or low level detection is used is selected by the
DREQS bit in DMDR.
When an external request is selected as an activation source, clear the DDR bit to 0 and set the
ICR bit to 1 for the corresponding pin. For details, see section 13, I/O Ports.
10.5.4
There are two types of bus access modes: cycle stealing and burst.
When an activation source is the auto request, the cycle stealing or burst mode is selected by bit
DTF0 in DMDR. When an activation source is the on-chip module interrupt or external request,
the cycle stealing mode is selected.
(1)
In cycle stealing mode, the DMAC releases the bus every time one unit of transfers (byte, word,
longword, or 1-block size) is completed. After that, when a transfer is requested, the DMAC
obtains the bus to transfer 1-unit data and then releases the bus on completion of the transfer. This
operation is continued until the transfer end condition is satisfied.
When a transfer is requested to another channel during a DMA transfer, the DMAC releases the
bus and then transfers data for the requested channel. For details on operations when a transfer is
requested to multiple channels, see section 10.5.8, Priority of Channels.
Activation by External Request
Cycle Stealing Mode
Bus Access Modes
Rev. 2.00 Oct. 21, 2009 Page 409 of 1454
Section 10 DMA Controller (DMAC)
REJ09B0498-0200