R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 978

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
(1)
During transmission, the output signals from the SCI (UART frames) are converted to IR frames
using the IrDA interface (see figure 19.37).
For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is
output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in
IrCR.
The high-level pulse width is defined to be 1.41 μs at minimum and (3/16 + 2.5%) × bit rate or
(3/16 × bit rate) +1.08 μs at maximum. For example, when the frequency of system clock φ is 20
MHz, a high-level pulse width of 1.6 µs can be specified because it is the smallest value in the
range greater than 1.41 µs.
For serial data of level 1, no pulses are output.
(2)
During reception, IR frames are converted to UART frames using the IrDA interface before
inputting to SCI. 0 is output when the high level pulse is detected while 1 is output when no pulse
is detected during one bit period. Note that a pulse shorter than the minimum pulse width of 1.41
μs is also regarded as a 0 signal.
Rev. 2.00 Oct. 21, 2009 Page 944 of 1454
REJ09B0498-0200
Transmission
Reception
Transmission
Bit
cycle
Start
bit
Start
bit
Figure 19.37 IrDA Transmission and Reception
0
0
1
1
0
0
UART frame
IR frame
1
1
0
0
Data
Data
0
0
Reception
1
1
Pulse width is 1.6 μs to
3/16 bit cycle
1
1
0
0
Stop
bit
Stop
bit
1
1

Related parts for R5F61665N50FPV