R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 312

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
9.10.5
Figure 9.38 shows a basic access timing of the DRAM space.
A basic bus cycle consists of four clock cycles: one precharge cycle (Tp), one row address output
cycle (Tr), and two column address output cycles (Tc1 and Tc2).
The RD signal is output to DRAM as an OE signal on a DRAM access. When DRAM with the
EDO page mode function is in use, connect the OE signal to the OE pin of the DRAM.
Rev. 2.00 Oct. 21, 2009 Page 278 of 1454
REJ09B0498-0200
Basic Timing
Figure 9.38 DRAM Basic Access Timing (RAS = 0 and CAST = 0)
Read
Write
Address bus
Data bus
Data bus
OE (RD)
OE (RD)
LUCAS
RD/WR
LLCAS
RAS
WE
WE
BS
Bφ
T
Row address
p
T
r
High
High
Column address
T
c1
T
c2