R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 193

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1)
The activation source for each DMAC channel is selected by DMRSR. The selected activation
source is input to the DMAC through the select circuit. When transfer by an on-chip module
interrupt is enabled (DTF1 = 1, DTF0 = 0, and DTE = 1 in DMDR) and the DTA bit in DMDR is
set to 1, the interrupt source selected for the DMAC activation source is controlled by the DMAC
and cannot be used as a DTC activation source or CPU interrupt source.
Interrupt sources that are not controlled by the DMAC are set for DTC activation sources or CPU
interrupt sources by the DTCE bit in DTCERA to DTCERF of the DTC.
Specifying the DISEL bit in MRB of the DTC generates an interrupt request to the CPU by
clearing the DTCE bit to 0 after the individual DTC data transfer.
Note that when the DTC performs a predetermined number of data transfers and the transfer
counter indicates 0, an interrupt request is made to the CPU by clearing the DTCE bit to 0 after the
DTC data transfer.
When the same interrupt source is set as both the DTC and DMAC activation source and CPU
interrupt source, the DTC and DMAC must be given priority over the CPU. If the IPSETE bit in
CPUPCR is set to 1, the priority is determined according to the IPR setting. Therefore, the CPUP
setting or the IPR setting corresponding to the interrupt source must be set to lower than or equal
to the DTCP and DMAP setting. If the CPU is given priority over the DTC or DMAC, the DTC or
DMAC may not be activated, and the data transfer may not be performed.
peripheral
Selection of Interrupt Sources
On-chip
interrupt
module
IRQ
Figure 7.6 Block Diagram of DTC, DMAC, and Interrupt Controller
Interrupt request
Interrupt request
clear signal
clear signal
Interrupt
Interrupt
request
request
Interrupt controller
DMAC
select
circuit
Select signal
Interrupt request
Clear signal
DTC/CPU
DMRSR_0 to DMRSR_3
DTCER
select
circuit
Select signal
Clear signal
Control signal
DMAC activation request signal
Clear signal
Rev. 2.00 Oct. 21, 2009 Page 159 of 1454
determination
DTC control
Priority
circuit
Section 7 Interrupt Controller
DTC activation request
vector number
CPU interrupt request
vector number
I, I2 to I0
signal
Clear
REJ09B0498-0200
DMAC
CPU
DTC