R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 56

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 1 Overview
Classification Pin Name
On-chip
emulator
Address bus
Data bus
Bus control
Rev. 2.00 Oct. 21, 2009 Page 22 of 1454
REJ09B0498-0200
TRST
TMS
TDI
TCK
TDO
D15 to D0
BREQ
BREQO
BACK
BS-A/BS-B
AS
AH
RD
(RD/WR-A)/(RD/WR-B) Output
LHWR
LLWR
LUB
LLB
A23 to A0
I/O
Input
Input
Input
Input
Output
Output
Input/
output
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Description
On-chip emulator pins or boundary scan pins. When the
EMLE pin is driven high, these pins are dedicated for the on-
chip emulator. When the EMLE pin is driven low and to mode
3, these pins are dedicated for the boundary scan mode.
Output pins for the address bits.
Input and output for the bidirectional data bus. These pins
also output addresses when accessing an address–data
multiplexed I/O interface space.
External bus-master modules assert this signal to request
the bus.
Internal bus-master modules assert this signal to request
access to the external space via the bus in the external bus
released state.
Bus acknowledge signal, which indicates that the bus has
been released.
Indicates the start of a bus cycle.
Strobe signal which indicates that the output address on the
address bus is valid in access to the basic bus interface or
byte control SRAM interface space.
This signal is used to hold the address when accessing the
address-data multiplexed I/O interface space.
Strobe signal which indicates that reading from the basic bus
interface space is in progress.
Indicates the direction (input or output) of the data bus.
Strobe signal which indicates that the higher-order byte (D15
to D8) is valid in access to the basic bus interface space.
Strobe signal which indicates that the lower-order byte (D7 to
D0) is valid in access to the basic bus interface space.
Strobe signal which indicates that the higher-order byte (D15
to D8) is valid in access to the byte control SRAM interface
space.
Strobe signal which indicates that the lower-order byte (D7 to
D0) is valid in access to the byte control SRAM interface
space.