R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 923

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note:
Bit
2
1
0
*
Bit Name
TEND
MPB
MPBT
Only 0 can be written, to clear the flag.
Initial
Value
1
0
0
R/W
R
R
R/W
Multiprocessor Bit Transfer
Description
Transmit End
This bit is set to 1 when no error signal is sent from the
receiving side and the next transmit data is ready to be
transferred to TDR.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Multiprocessor Bit
Not used in smart card interface mode.
Write 0 to this bit in smart card interface mode.
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
When both the TE and ERS bits in SCR are 0
When ERS = 0 and TDRE = 1 after a specified time
passed after completion of 1-byte data transfer. The
set timing depends on the register setting as follows:
When GM = 0 and BLK = 0, 2.5 etu after transmission
start
When GM = 0 and BLK = 1, 1.5 etu after transmission
start
When GM = 1 and BLK = 0, 1.0 etu after transmission
start
When GM = 1 and BLK = 1, 1.0 etu after transmission
start
When 0 is written to TEND after reading TEND = 1
When a TXI interrupt request is issued allowing
DMAC or DTC to write the next data to TDR
Rev. 2.00 Oct. 21, 2009 Page 889 of 1454
REJ09B0498-0200