R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 425

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
26
25
24
23, 22
21
20
Bit Name
RPTIE
ARS1
ARS0
⎯
SAT1
SAT0
Initial
Value
0
0
0
All 0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
Description
Repeat Size End Interrupt Enable
Enables/disables a repeat size end interrupt request.
In repeat transfer mode, when the next transfer is
requested after completion of a 1-repeat-size data
transfer while this bit is set to 1, the DTE bit in DMDR is
cleared to 0. At this time, the ESIF bit in DMDR is set to
1 to indicate that a repeat size end interrupt is
requested. Even when the repeat area is not specified
(ARS1 = 1 and ARS0 = 0), a repeat size end interrupt
after a 1-block data transfer can be requested.
In addition, in block transfer mode, when the next
transfer is requested after 1-block data transfer while
this bit is set to 1, the DTE bit in DMDR is cleared to 0.
At this time, the ESIF bit in DMDR is set to 1 to indicate
that a repeat size end interrupt is requested.
0: Disables a repeat size end interrupt
1: Enables a repeat size end interrupt
Area Select 1 and 0
Specify the block area or repeat area in block or repeat
transfer mode.
00: Specify the block area or repeat area on the source
01: Specify the block area or repeat area on the
10: Do not specify the block area or repeat area
11: Setting prohibited
Reserved
These bits are always read as 0 and cannot be
modified.
Source Address Update Mode 1 and 0
Select the update method of the source address
(DSAR). When DSAR is not specified as the transfer
source in single address mode, this bit is ignored.
00: Source address is fixed
01: Source address is updated by adding the offset
10: Source address is updated by adding 1, 2, or 4
11: Source address is updated by subtracting 1, 2, or 4
address
destination address
according to the data access size
according to the data access size
Rev. 2.00 Oct. 21, 2009 Page 391 of 1454
Section 10 DMA Controller (DMAC)
REJ09B0498-0200