R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1268

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 27 Clock Pulse Generator
Rev. 2.00 Oct. 21, 2009 Page 1234 of 1454
REJ09B0498-0200
Bit
13 to 11 ⎯
10
9
8
7
6
5
4
Bit Name
ICK2
ICK1
ICK0
⎯
PCK2
PCK1
PCK0
Initial
Value
All 0
0
1
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
Although these bits are readable/writable, only 0 should
be written to.
System Clock (Iφ) Select
These bits select the frequency of the system clock
provided to the CPU, EXDMAC, DMAC, and DTC. The
ratio to the input clock is as follows:
ICK (2:0) MD_CLK = 0
000:
001:
010:
011:
1XX:
The frequencies of the peripheral module clock and
external bus clock change to the same frequency as the
system clock if the frequency of the system clock is
lower than that of the two clocks.
Reserved
Although this bit is readable/writable, only 0 should be
written to.
Peripheral Module Clock (Pφ) Select
These bits select the frequency of the peripheral
module clock. The ratio to the input clock is as follows:
PCK (2:0) MD_CLK = 0
000:
001:
010:
011:
1XX:
The frequency of the peripheral module clock should be
lower than that of the system clock. Though these bits
can be set so as to make the frequency of the
peripheral module clock higher than that of the system
clock, the clocks will have the same frequency in reality.
Setting prohibited
Setting prohibited
× 1/2
× 4
× 2
× 1
× 1/2
× 4
× 2
× 1
MD_CLK = 1
× 2
× 1
× 1/2
Setting prohibited
MD_CLK = 1
× 2
× 1
× 1/2
Setting prohibited