R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 530

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC)
When a block area (repeat area) is set for the source address in block transfer mode (or repeat
transfer mode), the source address is restored to the transfer start address at the end of block-size
(repeat-size) transfer and is not affected by address updating.
When an extended repeat area is set for the source address, the operation conforms to that setting.
The upper addresses set for the extended repeat area is fixed, and is not affected by address
updating.
When EDSAR is read during a transfer operation, a longword access must be used. During a
transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the
correct values may not be read if the upper and lower words are read separately. Do not write to
EDSAR for a channel on which a transfer operation is in progress.
(2)
EXDMA Destination Address Register (EDDAR)
When the EDDAR address is accessed as the transfer destination, the EDDAR value is output, and
then EDDAR is updated with the address to be accessed next.
Bits DAT1 and DAT0 in EDACR specify incrementing or decrementing. The address is fixed
when DAT1 and DAT0 = B′00, incremented by offset register value when DAT1 and DAT0 =
B′01, incremented when DAT1 and DAT0 = B′10, and decremented when DAT1 and DAT0 =
B′11. (The increment or decrement value is determined by the data access size.)
The DTSZ1 and DTSZ0 bits in EDMDR set the data access size. When DTSZ1 and DTSZ0 =
B′00, the data is byte-size and the address is incremented or decremented by 1. When DTSZ1 and
DTSZ0 = B′01, the data is word-size and the address is incremented or decremented by 2. When
DTSZ1 and DTSZ0 = B′10, the data is longword-size and the address is incremented or
decremented by 4. When a word-size or longword-size is specified but the destination address is
not at the word or longword boundary, the data is divided into bytes or words for writing. When a
word or a longword is divided for writing, the address is incremented or decremented by 1 or 2
according to an actual byte- or word-size written. After a word-size or longword-size write, the
address is incremented or decremented to or from the write start address according to the setting of
SAT1 and SAT0.
When a block area (repeat area) is set for the destination address in block transfer mode (or repeat
transfer mode), the destination address is restored to the transfer start address at the end of block-
size (repeat-size) transfer and is not affected by address updating.
When an extended repeat area is set for the destination address, the operation conforms to that
setting. The upper addresses set for the extended repeat area is fixed, and is not affected by
address updating.
Rev. 2.00 Oct. 21, 2009 Page 496 of 1454
REJ09B0498-0200