R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1000

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 USB Function Module (USB)
20.3.2
IFR1, together with interrupt flag registers 0 and 2 (IFR0 and IFR2), indicates interrupt status
information required by the application. When an interrupt source is generated, the corresponding
bit is set to 1. And then this bit, in combination with interrupt enable register 1 (IER1), generates
an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
Rev. 2.00 Oct. 21, 2009 Page 966 of 1454
REJ09B0498-0200
Bit
7
6
5
4
3
2
1
Bit
Bit Name
Initial Value
R/W
Interrupt Flag Register 1 (IFR1)
Bit Name
⎯
—
—
—
VBUS MN
EP3 TR
EP3 TS
⎯
R
7
0
Initial
Value
0
0
0
0
0
0
0
⎯
R
6
0
R/W
R
R
R
R
R
R/W
R/W
⎯
R
5
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
This is a status bit which monitors the state of the
VBUS pin.
This bit reflects the state of the VBUS pin and
generates no interrupt request. This bit is always 0
when the PULLUP_E bit in DMA is 0.
EP3 Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 3 is
received from the host. A NACK handshake is returned
to the host until data is written to the FIFO buffer and
packet transmission is enabled.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
EP3 Transmit Complete
This bit is set when data is transmitted to the host from
endpoint 3 and an ACK handshake is returned.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
⎯
R
4
0
VBUS MN
R
3
0
EP3 TR
R/W
2
0
EP3 TS
R/W
1
0
VBUSF
R/W
0
0