R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1009

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.3.11 EP0o Data Register (EPDR0o)
EPDR0o is an 8-byte receive FIFO buffer for endpoint 0. EPDR0o holds endpoint 0 receive data
other than setup commands. When data is received successfully, EP0oTS in interrupt flag register
0 is set, and the number of receive bytes is indicated in the EP0o receive data size register. After
the data has been read, setting EP0oRDFN in the trigger register enables the next packet to be
received. This FIFO buffer can be initialized by means of BP0oCLR in the FCLR register.
20.3.12 EP0s Data Register (EPDR0s)
EPDR0s is an 8-byte FIFO buffer specifically for receiving endpoint 0 setup commands. Only the
setup command to be processed by the application is received. When command data is received
successfully, the SETUPTS bit in interrupt flag register 0 is set.
As a latest setup command must be received in high priority, if data is left in this buffer, it will be
overwritten with new data. If reception of the next command is started while the current command
is being read, command reception has priority, the read by the application is forcibly stopped, and
the read data is invalid.
Bit
7 to 0
Bit
7 to 0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Name
D7 to D0
Bit Name
D7 to D0
D7
D7
R
R
7
0
7
0
Initial
Value
All 0
Initial
Value
All 0
D6
D6
R
R
6
0
6
0
R/W
R
R/W
R
D5
D5
R
R
5
0
5
0
Description
Data register for control-out transfer
Description
Data register for storing the setup command at the
control-out transfer
D4
D4
R
R
4
0
4
0
D3
D3
R
R
3
0
3
0
Rev. 2.00 Oct. 21, 2009 Page 975 of 1454
Section 20 USB Function Module (USB)
D2
D2
R
R
2
0
2
0
D1
D1
R
R
1
0
1
0
REJ09B0498-0200
D0
D0
R
R
0
0
0
0