R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 365

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
(3)
Refresh and All-Module Clock Stop Mode
This LSI is entered in all-module clock stop mode by the following operation: Stop the clocks of
all on-chip peripheral modules by setting the ACSE bit in MSTPCRA to 1 (MSTPCRA,
MSTPCRB = H'FFFFFFFF) or run only the 8-bit timer (MSTPCRA, MSTPCRB = H'F[C to
F]FFFFFF), then execute the SLEEP instruction to enter the sleep mode.
In all-module clock stop mode, clocks for the bus controller and I/O ports are stopped. Since the
clock for the bus controller is stopped, an auto-refresh cycle cannot be performed. When external
SDRAM is used and the contents of the SDRAM in sleep mode should be held, clear the ACSE bit
in MSTPCE to 0.
For details, see section 28.2.2, Module Stop Control Registers A and B (MSTPCRA and
MSTPCRB).
9.11.14 Setting SDRAM Mode Register
To use SDRAM, the mode register must be specified after a power-on reset.
Setting the MRSE bit in SDCR to 1 enables the SDRAM mode register setting. After this, write to
the SDRAM space in bytes.
When the value to be set in the SDRAM mode register is x, write to the following memory
location (address). The value of x is written to the SDRAM mode register.
• H'4000000/H'400000 + x for 8-bit bus SDRAM
• H'4000000/H'400000 + 2x for 16-bit bus SDRAM
The SDRAM mode register latches the address signals when the MRS command is issued.
This LSI does not support the burst read/burst write mode of SDRAM. When setting the SDRAM
mode register, use the burst read/single write mode and set the burst length to 1. Setting in the
SDRAM mode register must be consistent with that in the bus controller.
Rev. 2.00 Oct. 21, 2009 Page 331 of 1454
REJ09B0498-0200