R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 101

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
2.8.5
• Register indirect with post-increment—@ERn+
• Register indirect with pre-decrement—@−ERn
• Register indirect with pre-increment—@+ERn
• Register indirect with post-decrement—@ERn−
using this addressing mode, data to be written is the contents of the general register after
calculating an effective address. If the same general register is specified in an instruction and two
effective addresses are calculated, the contents of the general register after the first calculation of
an effective address is used in the second calculation of an effective address.
Example 1:
MOV.W
When ER0 before execution is H'12345678, H'567A is written at H'12345678.
The operand value is the contents of a memory location which is pointed to by the contents of
an address register (ERn). ERn is specified by the register field of the instruction code. After
the memory location is accessed, 1, 2, or 4 is added to the address register contents and the
sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or
4 for longword access.
The operand value is the contents of a memory location which is pointed to by the following
operation result: the value 1, 2, or 4 is subtracted from the contents of an address register
(ERn). ERn is specified by the register field of the instruction code. After that, the operand
value is stored in the address register. The value subtracted is 1 for byte access, 2 for word
access, or 4 for longword access.
The operand value is the contents of a memory location which is pointed to by the following
operation result: the value 1, 2, or 4 is added to the contents of an address register (ERn). ERn
is specified by the register field of the instruction code. After that, the operand value is stored
in the address register. The value added is 1 for byte access, 2 for word access, or 4 for
longword access.
The operand value is the contents of a memory location which is pointed to by the contents of
an address register (ERn). ERn is specified by the register field of the instruction code. After
the memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and
the remainder is stored in the address register. The value subtracted is 1 for byte access, 2 for
word access, or 4 for longword access.
Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment,
or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn−
R0, @ER0+
Rev. 2.00 Oct. 21, 2009 Page 67 of 1454
REJ09B0498-0200
Section 2 CPU

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