HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 99

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.3.3
3.8.3.4
July 2009
Order Number: 318378-005US
PAM2 - Programmable Attribute Map Register 2
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0C 8000h -0C FFFFh.
PAM3 - Programmable Attribute Map Register 3
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0D 0000h - 0D 7FFFh.
Device:
Function:
Offset:
Device:
Function:
Offset:
5:4
3:2
1:0
7:6
5:4
3:2
1:0
Bit
Bit
®
Attr
Attr
RW
RW
RW
RW
RV
RV
RV
5100 MCH Chipset
16
0
5Ah
16
0
5Bh
Default
Default
00
00
00
00
00
00
00
ESIENABLE1: 0C4000-0C7FFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0C4000 to 0C7FFF
Bit5 = Write enable, Bit4 = Read enable.
Encoding: Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Reserved
LOENABLE1: 0C0000-0C3FFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0C0000 to 0C3FFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding: Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Reserved
ESIENABLE2: 0CC000-0CFFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0CC000-0CFFFF.
Bit5 = Write enable, Bit4 = Read enable.
Encoding: Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Reserved
LOENABLE2: 0C8000-0CBFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0C8000-0CBFFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding: Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
99