HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 102

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.3.8
3.8.3.9
Intel
Datasheet
102
®
5100 Memory Controller Hub Chipset
SMRAMC - System Management RAM Control Register
The SMRAMC register controls how accesses to Compatible and Extended SMRAM
spaces are treated. The Open, Close, and Lock bits function only when
EXSMRC.G_SMRAME bit is set to a 1. Also, the OPEN bit must be reset before the LOCK
bit is set.
EXSMRC - Extended System Management RAM Control Register
The Extended SMRAM register controls the configuration of Extended SMRAM space.
The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM
memory space that is above 1 MByte.
Device:
Function:
Offset:
Device:
Function:
Offset:
2:0
Bit
Bit
7
6
5
4
3
7
6
Attr
RWL
RWL
Attr
RWL
RW
RO
RO
RV
RV
16
0
61h
16
0
62h
Default
Default
010
0
0
0
0
0
0
0
Reserved
D_OPEN: SMM Space Open
When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made visible even
when SMM decode is not active. This is intended to help BIOS initialize SMM
space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at
the same time. This register can be locked by D_LCK.
D_CLS: SMM Space Closed
When D_CLS = 1 SMM space DRAM is not accessible to data references, even
if SMM decode is active. Code references may still access SMM space DRAM.
This will allow SMM software to reference through SMM space to update the
display even when SMM is mapped over the VGA range. Software should
ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. Note that
the D_CLS bit only applies to Compatible SMM space.
D_LCK: SMM Space Locked
When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK, D_OPEN,
C_BASE_SEG, H_SMRAM_EN, ESMMTOP, TSEG_SZ and TSEG_EN become read
only. D_LCK can be set to 1 via a normal configuration space write but can
only be cleared by a Full Reset. The combination of D_LCK and D_OPEN
provide convenience with security. The BIOS can use the D_OPEN function to
initialize SMM space and then use D_LCK to “lock down” SMM space in the
future so that no application software (or BIOS itself) can violate the integrity
of SMM space, even if the program has knowledge of the D_OPEN function.
Reserved
C_BASE_SEG: Compatible SMM Space Base Segment
This field indicates the location of legacy SMM space. SMM DRAM is not
remapped. It is simply made visible if the conditions are right to access SMM
space, otherwise the access is forwarded to ESI/VGA. Since the MCH supports
only the SMM space between A 0000h and B FFFFh, this field is hardwired to
010.
H_SMRAME: Enable High SMRAM
Controls the SMM memory space location (i.e., above 1 MByte or below 1
MByte) When G_SMRAME is 1 and H_SMRAME is set to 1, the high SMRAM
memory space is enabled. SMRAM accesses within the range FEDA_0000h to
FEDB FFFFh are remapped to DRAM addresses within the range 000A_0000h
to 000B_FFFFh. Once D_LCK has been set, this bit becomes read only.
MDAP: MDA Present
Since the MCH does not support MDA, this bit has no meaning.
Intel
®
Description
Description
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009