HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 36

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 5.
Intel
Datasheet
36
®
5100 Memory Controller Hub Chipset
Processor Front Side Bus 0 Signals (Sheet 2 of 5)
FSB0BINIT#
FSB0BNR#
FSB0BPM[5:4]#
FSB0BPRI#
FSB0BREQ[1:0]#
Signal Name
I/O
I/O
I/O
O
I/O
Type
Processor 0 Bus Initialization:
FSB0BINIT# may be observed and driven by all processor FSB agents. If the
FSB0BINIT# driver is enabled during power on configuration, FSB0BINIT# is
asserted to signal any bus condition that prevents reliable future operation.
If FSB0BINIT# observation is enabled during power-on configuration and
FSB0BINIT# is sampled asserted, symmetric agents reset their bus LOCK#
activity and bus request arbitration state machines. The bus agents do not
reset their I/O Queue (IOQ) and transaction tracking state machines upon
observation of FSB0BINIT# assertion. Once the FSB0BINIT# assertion has
been observed, the bus agents will re-arbitrate for the FSB and attempt
completion of their bus queue and IOQ entries.
If FSB0BINIT# observation is disabled during power-on configuration, a priority
agent may handle an assertion of FSB0BINIT# as appropriate to the error
handling architecture of the system.
Processor 0 Block Next Request:
FSB0BNR# is used to assert a bus stall by any bus agent who is unable to
accept new bus transactions. During a bus stall, the current bus owner cannot
issue any new transactions.
Since multiple agents might need to request a bus stall at the same time,
FSB0BNR# is a wired-OR signal which must connect the appropriate pins of all
processor FSB agents. In order to avoid wired-OR glitches associated with
simultaneous edge transitions driven by multiple drivers, FSB0BNR# is
activated on specific clock edges and sampled on specific clock edges.
FSB0BNR# is used to block the current request bus owner from issuing a new
request. This signal is used to dynamically control the processor bus pipeline
depth.
Processor 0 Breakpoint Monitor/Debug Bus:
FSB0BPM[5:0]# are breakpoint and performance monitor signals. They are
outputs from the processor which indicate the status of breakpoints and
programmable counters used for monitoring processor performance.
FSB0BPM[5:0]# should connect the appropriate pins of all FSB agents.
FSB0BPM[4]# provides PRDY# (Probe Ready) functionality for the TAP port.
PRDY# is a processor output used by debug tools to determine processor debug
readiness.
FSB0BPM[5]# provides PREQ# (Probe Request) functionality for the TAP port.
PREQ# is used by debug tools to request debug operation of the processors.
FSB0BPM[5:4]# must be bussed to all bus agents. Please refer to the
appropriate platform design guidelines for more detailed information.
Processor 0 Priority Agent Bus Request:
FSB0BPRI# is used to arbitrate for ownership of the processor FSB. It must
connect the appropriate pins of all processor FSB agents. Observing FSB0BPRI#
active (as asserted by the priority agent) causes all other agents to stop issuing
new requests, unless such requests are part of an ongoing locked operation.
The priority agent keeps FSB0BPRI# asserted until all of its requests are
completed, then releases the bus by deasserting FSB0BPRI#.
The MCH is the only Priority Agent on the processor bus. It asserts this signal to
obtain ownership of the address bus. This signal has priority over symmetric
bus requests and cause the current symmetric owner to stop issuing new
transactions unless the FSB0LOCK# signal was asserted.
Processor 0 Bus Requests:
The MCH pulls the FSB0BREQ[0]# signal low during RESET#. The signal is
sampled by the processor on the active-to-inactive transition of FSB0RESET#.
Intel
Description
®
5100 MCH Chipset—Signal Description
Order Number: 318378-005US
July 2009