HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 302

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Note:
Note:
5.8
Intel
Datasheet
302
®
5100 Memory Controller Hub Chipset
wants to “flush” all MSI writes from the root port, i.e., guarantee that all the MSI writes
pending in the MCH from the root port have been delivered to the local APIC in the
processor. To accomplish this flush operation, OS can perform a configuration read to,
say, the VendorID/DeviceID register of the root port and the expectation is that the
completion for this read will flush all the previously issued memory writes. The reason
the OS wants to flush is for cases where an interrupt source (like a root port) is being
retargeted to a different processor and OS needs to flush any MSI that is already
pending in the fabric that is still targeting the old processor.
As a case in point, reads to the Intel
configuration spaces will not generally guarantee ordering of internal MSIs from a root
port/DMA Engine device as required. This is because the Intel
a configuration ring methodology which houses the registers for the various PCI
Express* ports, Memory Controller (MC), DMA Engine, Dfx etc. and it operates
independently of the MSI/interrupt generation logic. Thus any configuration ring access
targeting a PCI Express* port registers will not necessarily order and align with the
internal MSIs.
Solution: To mitigate this problem and enforce ordering of the MSIs, the Intel
MCH Chipset will implement a “pending MSI signal” that is broadcast from the MSI/PCI
Hot Plug* blocks to the Coherency Engine (CE) and thereby block the configuration
request (non-posted) till all the MSI gets committed. Software will ensure that it will
block future MSI generation for that device when it issues the configuration read for
that device.
The CE will block sending any completion with the new bit-slice bit set when any of the
pending MSI wires are asserted. CE will not block other transactions or completions
during the block. When the pending MSI wires are deasserted, CE will be able to send
the configuration completions.
The Intel
configuration access completions (MMCFG or CFC/CF8) if there is a pending internally
generated MSI within the Intel
DMA Engine or the HotPlug-Pwr-Mgr-PEX Error block.
The pending MSI signal will be deasserted after fetch-completion is asserted for the
MSI from CE, i.e., global visibility is guaranteed on the FSB. Then release the
configuration block and allow the configuration completion to flow through. This
approach will order the MSI and then send the non-posted configuration for that
device.
CE will add a bit-slice (one bit per table entry) to track processor initiated MCH
configuration access in CE transaction table.
Inbound configuration access will not set this bit.
Internal MSIs cannot be continuously generated since the corresponding status register
field needs to be cleared by software through configuration access before a new MSI
can be asserted.
Software Guidance for MSI Handling
There are two conditions under which the MCH expects software to handle Message
Signaled Interrupts (MSI) appropriately. The first is if one or more interrupt status bits
are set to ‘1’ and a new bit gets set to ‘1.’ The MCH will send an MSI for the new bit.
This may cause extraneous Interrupt Service Routine (ISR) calls. The second condition
occurs when one or more interrupt status bits are set to ‘1’ and software clears some
(but not all) bits. The MCH will not send an MSI for the remaining uncleared bits. This
may cause lost interrupts.
®
5100 MCH Chipset Coherency Engine (CE) will block processor initiated MCH
®
5100 MCH Chipset. MSIs could be generated from the
®
5100 MCH Chipset PCI Express* (internal)
Intel
®
5100 MCH Chipset—Functional Description
®
Order Number: 318378-005US
5100 MCH Chipset uses
®
July 2009
5100