HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 370

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 123.
Intel
Datasheet
370
F9
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
Notes:
1.
2.
ERR #
MCH
in
®
5100 Memory Controller Hub Chipset
IO3 error logging in Intel
ECN (Dec. 2004). However, PEXLNKSTS.TERR provides training indication.
Aliased uncorrectable errors are uncorrectable errors that masquerades as correctable errors to the Memory Controller.
FSB protocol
Error
Source Address
Error
Destination
Address Error
Next Descriptor
Address Error
Descriptor Error
Chain Address
Value Error
CHANCMD Error
Chipset Data
Parity error
Error Name
Intel
®
5100 Memory Controller Hub Chipset Error List (Sheet 2 of 7)
MCH detected FSB protocol
error, for example, HITM
on BIL and HITM on EWB
and HITM on BLW (lock
write).
The DMA channel sets this
bit indicating that the
current descriptor has an
illegal source address.
The DMA channel sets this
bit indicating that the
current descriptor has an
illegal destination address.
The DMA channel sets this
bit indicating that the next
descriptor in the link list
has an illegal address.
(including alignment error,
i.e., not on 64B boundary)
The DMA channel sets this
bit indicating that the
current transfer has
encountered an error (not
otherwise covered under
other DMA error bits)
when executing a DMA
descriptor.
The DMA channel sets this
bit indicating that the
CHAINADDR register has
an illegal address including
an alignment error (not on
a 64-byte boundary).
The DMA channel sets this
bit indicating that a write
to the CHANCMD register
contained an invalid value
(e.g., more than one
command bit set)
The DMA channel sets this
bit indicating that there is
a data parity error during a
read/write operation of a
given DMA descriptor.
®
5100 MCH Chipset has been defeatured due to PCI Express* Base Specification, Rev. 1.0a
Definition
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Error
Type
Channel Completion enable)
by taking a snap shot of the
the runtime addresses that
NERR_FAT_FSB. NRECFSB,
NRECADDRH, NRECADDRL
SADDR and DADDR will be
when an error is met. The
respective register fields
FERR_CHANCMP (Check
FERR_TRANSFER_SIZE,
FERR_DESC_CTRL,
the DMA Engine is
Intel
FERR_CHANERR/
NERR_CHANERR,
FERR_CHANCMD,
FERR_CHANSTS,
FERR_FAT_FSB/
FERR_DADDR,
FERR_SADDR,
FERR_NADDR,
Log Register
for FERR only.
executing
®
Log
5100 MCH Chipset—Functional Description
Order Number: 318378-005US
Complete transaction on
FSB with response (IWB as
in the example)
Halt DMA Engine
Halt DMA Engine
Halt DMA Engine
An illegal next descriptor
address flagged by the
system Address decoder,
which the DMA Engine
encounters in the current
descriptor after having
successfully completed the
data transfer for the current
descriptor including any
associated completions/
interrupts
Halt DMA Engine
Halt DMA Engine
Halt DMA Engine
Halt DMA Engine
Cause/Actions
July 2009