HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 255

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.12.0.11
3.12.0.12
3.12.0.13
3.12.0.14
July 2009
Order Number: 318378-005US
The offset indicates where the Stream ID priority Mapping register for port 2 resides in
the MMIO space.
STRMMAP_OFFSET3: Stream Priority Mapping Offset Register
The offset indicates where the Stream ID priority Mapping register for port 3 resides in
the MMIO space.
PORTPRI2: Port Priority Register
PORTPRI3: Port Priority Register
STRM_COMP[3:2] - Stream Priority Compatibility Register
Offset:
Offset:
Offset:
Offset:
15:2
15:1
1:0
7:4
3:0
7:4
3:0
Bit
Bit
Bit
Bit
0
Attr
Attr
Attr
Attr
RO
RO
RO
RO
RV
RV
RV
RV
®
5100 MCH Chipset
398h
31Ah
39Ah
39Ch, 31Ch
Default
Default
Default
Default
0h
0h
0h
0h
0h
0
0
0
Strmid_offset: Offset of Stream ID Map
The Intel
field is set to a Null pointer.
Reserved
Reserved
Port_pri: Port Priority
The Intel
register will consistently return zero.
Reserved
Port_pri: Port Priority
The Intel
register will consistently return zero.
Reserved
v1_comp: v1 Compatibility
The Intel
2 and 3. Hence, it is not compatible with DMA Engine software and is hardwired to
0.
®
®
®
®
5100 MCH Chipset does not implement stream priority and hence this
5100 MCH Chipset does not implement port priority for port 2 and this
5100 MCH Chipset does not implement port priority for port 3 and this
5100 MCH Chipset does not support Stream Priority operation for ports
Description
Description
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
255