HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 164

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.12.14
3.8.12.15
3.8.12.16
Intel
Datasheet
164
®
5100 Memory Controller Hub Chipset
HDRLOG3[7:2,0] - Header Log 3
This register contains the fourth 32 bits of the header log.
RPERRCMD[7:2,0] - Root Port Error Command
This register controls behavior upon detection of errors.
RPERRSTS[7:2,0] - Root Error Status Register
The Root Error Status register reports status of error messages (ERR_COR,
ERR_NONFATAL, and ERR_FATAL) received by the Root Complex in the MCH, and errors
detected by the Root Port itself (which are treated conceptually as if the Root Port had
sent an error message to itself). The ERR_NONFATAL and ERR_FATAL messages are
grouped together as uncorrectable. Each correctable and uncorrectable (Non-fatal and
Fatal) error source has a first error bit and a next error bit associated with it
respectively. When an error is received by a Root Complex, the respective first error bit
is set and the Requestor ID is logged in the Error Source Identification register. A set
individual error status bit indicates that a particular error category occurred; software
may clear an error status by writing a 1 to the respective bit. If software does not clear
the first reported error before another error message is received of the same category
(correctable or uncorrectable), the corresponding next error status bit will be set but
the Requestor ID of the subsequent error message is discarded. The next error status
bit may be cleared by software by writing a 1 to the respective bit as well. This register
is updated regardless of the settings of the Root Control register in
“PEXRTCTRL[7:2,0] - PCI Express* Root Control Register”
register defined in
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
31:27
31:0
31:3
Bit
Bit
Bit
2
1
0
ROST
Attr
Attr
Attr
RW
RW
RW
RV
RO
7-2, 0
0
128h
7-2, 0
0
12Ch
7-2, 0
0
130h
Default
Default
Section 3.8.12.15, “RPERRCMD[7:2,0] - Root Port Error Command.”
Default
0h
0h
0h
0
0
0
HDRLOGDW3: Header of TLP (DWORD 3) associated with error
Reserved
EN_FAT_ERR: FATAL Error Reporting Enable
Enable interrupt on fatal errors when set.
EN_NONFAT_ERR: Non-FATAL Error Reporting Enable
Enable interrupt on a non-fatal (uncorrectable) error when set
EN_CORR_ERR: Correctable Error Reporting Enable
Enable interrupt on correctable errors when set
ADVERR_INT_MSG_NUM: Advanced Error Interrupt Message Number
Advanced Error Interrupt Message Number offset between base message
data an the MSI message if assigned more than one message number to
be used of any status in this capability.
Intel
®
Description
5100 MCH Chipset—Register Description
Description
Description
and the Root Error Command
Order Number: 318378-005US
Section 3.8.11.12,
July 2009