HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 135

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.9.2
July 2009
Order Number: 318378-005US
PMCSR[7:2,0] - Power Management Control and Status Register
This register provides status and control information for PM events in the PCI Express*
port of the MCH.
Device:
Function:
Offset:
Device:
Function:
Offset:
31:27
24:22
18:16
31:24
15:8
7:0
Bit
Bit
26
25
21
20
19
23
®
Attr
RO
RO
RO
RO
RO
RO
RO
RO
RO
RV
Attr
5100 MCH Chipset
RO
RO
7-2, 0
0
50h
7-2, 0
0
54h
Default
11001
010
58h
01h
0h
Default
0
0
0
0
0
00h
0h
PMES: PME Support
Identifies power states in the Intel
“Assert_PMEGPE/Deassert_PMEGPE” message. Bits 31, 30 and 27 must be set
to ‘1’ for PCI-to-PCI bridge structures representing ports on root complexes.
The definition of these bits is taken from the PCI Bus Power Management
Interface Specification, revision 1.1.
XXXX1b - Assert_PMEGPE/Deassert_PMEGPE can be sent from D0
XXX1Xb - Assert_PMEGPE/Deassert_PMEGPE can be sent from D1
(Not supported by Intel
XX1XXb - Assert_PMEGPE/Deassert_PMEGPE can be sent from D2
(Not supported by Intel
X1XXXb - Assert_PMEGPE/Deassert_PMEGPE can be sent from D3 hot
(Supported by Intel
1XXXXb - Assert_PMEGPE/Deassert_PMEGPE can be sent from D3 cold
(Not supported by Intel
D2S: D2 Support
The Intel
D1S: D1 Support
The Intel
AUXCUR: AUX Current
DSI: Device Specific Initialization
Reserved.
PMECLK: PME Clock
This field is hardwired to 0h as it does not apply to PCI Express*.
VER: Version
This field is set to 2h as version number from the PCI Express* Base
Specification, Rev. 1.0a.
NXTCAPPTR: Next Capability Pointer
This field is set to offset 58h for the next capability structure (MSI) in the PCI
2.3 compatible space.
CAPID: Capability ID
Provides the PM capability ID assigned by PCI-SIG.
Data: Data
Data read out based on data select (DSEL). Refer to section 3.2.6 of PCI
Bus Power Management Interface Specification, revision 1.1, for details.
This is not implemented in the Power Management capability for the Intel
5100 MCH Chipset and is hardwired to 0h.
BPCCEN: Bus Power/Clock Control Enable
This field is hardwired to 0h as it does not apply to PCI Express*.
®
®
5100 MCH Chipset does not support power management state D2.
5100 MCH Chipset does not support power management state D1.
®
5100 MCH Chipset)
®
®
®
5100 MCH Chipset)
5100 MCH Chipset)
5100 MCH Chipset)
Description
®
Description
Intel
5100 MCH Chipset which can send an
®
5100 Memory Controller Hub Chipset
Datasheet
135
®