HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 373

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
Table 123.
July 2009
Order Number: 318378-005US
IO6
IO7
IO8
IO9
IO10
IO11
IO12
IO13
IO14
IO15
IO16
IO17
Notes:
1.
2.
ERR #
MCH
in
IO3 error logging in Intel
ECN (Dec. 2004). However, PEXLNKSTS.TERR provides training indication.
Aliased uncorrectable errors are uncorrectable errors that masquerades as correctable errors to the Memory Controller.
PCI Express* -
Completion
Timeout
PCI Express* -
Completer Abort
PCI Express* -
Unexpected
Completion
Error
PCI Express* -
Malformed TLP
PCI Express* -
Receive Buffer
Overflow Error
PCI Express* -
Received
NonFatal Error
Message
PCI Express* -
Receiver Error
PCI Express* -
Bad TLP Error
PCI Express* -
BAD DLLP
PCI Express* -
Replay_Num
Rollover
PCI Express* -
Replay Timer
Timeout
PCI Express* -
Received
Correctable
Error Message
Error Name
Intel
®
5100 Memory Controller Hub Chipset Error List (Sheet 5 of 7)
Pending transaction did
not complete within the
time limit.
Received return CA status
for unknown error on the
component. This is
equivalent to a target
abort on PCI.
Received a Completion
RequestorID that matches
the requestor but the Tag
does not match any
pending entries.
Received a transaction
layer packet that does not
follow the TLP formation
rules.
Receiver gets more data or
transactions than credits
allow.
MCH received a NonFatal
error message from the
south bridge.
Log header of packets with
errors
Received bad CRC or a bad
sequence number in a
transport layer packet.
Received bad CRC in a
data link layer packet.
Replay maximum count for
the Retry Buffer has been
exceeded.
Replay timer timed out
waiting for an Ack or Nak
DLLP.
MCH received a
correctable error message
from the south bridge.
®
5100 MCH Chipset
®
5100 MCH Chipset has been defeatured due to PCI Express* Base Specification, Rev. 1.0a
Definition
=UnCorr
=UnCorr
=UnCorr
=UnCorr
UNCERR
UNCERR
UNCERR
UNCERR
UNCERR
Default
Default
Default
Default
Default
(Check
(Check
(Check
(Check
(Check
UnCorr
=Fatal
Error
Type
SEV)
SEV)
SEV)
SEV)
SEV)
Corr
Corr
Corr
Corr
Corr
Corr
and other I/O errors based
respective Error types and
Log PEX_FAT_FERR/NERR
Log UNCERRSTS for their
Log the first error pointer
Log CORERRSTS for their
Log PEXDEVSTS for IO12
or PEX_NF_COR_FERR/
Log RPERRSTS for IO1,
Severity (UNCERRSEV)
respective Error Types.
respective Error Types.
NERR based on their
for UNCERRSTS in
IO11 and IO17.
on UNCERRSEV
AERRCAPCTRL.
Log Register
Intel
®
5100 Memory Controller Hub Chipset
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Log CORERRSTS for their
respective Error Types.
Log CORERRSTS for their
respective Error Types.
Log CORERRSTS for their
respective Error Types.
Log CORERRSTS for their
respective Error Types.
Log CORERRSTS for their
respective Error Types.
Log CORERRSTS for their
respective Error Types.
Log CORERRSTS for their
respective Error Types.
Cause/Actions
Datasheet
373