HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 239

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
July 2009
Order Number: 318378-005US
Device:
Function:
Offset:
15
14
13
12
11
10
9
8
7
6
5
4
3
Bit
RO
RO
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RO
RWCST
RWCST
RWCST
RWCST
®
Attr
5100 MCH Chipset
8
0
BCh
0
0
0
0
0
0
0
0
0
0
0
0
0
Default
NERR_Unaffiliated_Error_DMA15
The Intel
NERR_Soft_Error_DMA14
The Intel
errors.
NERR_Interrupt_Configuration Error_DMA13
The DMA channel sets this bit indicating that the interrupt registers were not
configured properly when the DMA channel attempted to generate an interrupt.
NERR_Completion_Address Error_DMA12
The DMA channel sets this bit indicating that the completion address register
was configured to an illegal address or has not been configured. This address
will be checked and set by the DMA Engine during execution, i.e., when the
completion address is fetched for status update.
NERR_Descriptor_Length Error_DMA11
The DMA channel sets this bit indicating that the current transfer has an illegal
length field value (either zero or exceeded the maximum length allowed in the
XFERCAP.trans_cap field in
NERR_Descriptor_Control_Error_DMA10
The DMA channel sets this bit indicating that the current descriptor has an
illegal control field value in the “desc_control” field.
NERR_Write_Data_Error_DMA9
The DMA channel sets this bit indicating that the current transfer has
encountered an error while writing the destination data (e.g., no space available
in DM). When this bit has been set, the address of the failed descriptor is in the
Channel Status register.
NERR_Read_Data_Error_DMA8
The DMA channel sets this bit indicating that the current transfer has
encountered an error while accessing the source data. (e.g., starvation) When
this bit has been set, the address of the failed descriptor is in the Channel
Status register.
NERR_DMA_Data_Parity Error_DMA7
The DMA Engine has no internal parity checking and is hard-wired to 0.
NERR_Chipset_Data_Parity_Error_DMA6
The DMA channel sets this bit indicating that the current transfer has
encountered a parity error reported by the chipset. When this bit has been set,
the address of the failed descriptor is in the Channel Status register.
In the case of Source data error, NERR*DMA8 is also set.
In the case of Destination data error, NERR*DMA9 is also set
NERR_CHANCMD_Error_DMA5
The DMA channel sets this bit indicating that a write to the CHANCMD register
contained an invalid value (e.g., more than one command bit set).
NERR_Chain Address_Value_Error_DMA4
The DMA channel sets this bit indicating that the CHAINADDR register has an
illegal address including an alignment error (not on a 64-byte boundary). This
address will be checked and set by the DMA Engine during execution, i.e., when
the initial descriptor is fetched
NERR_Descriptor_Error_DMA3
The DMA channel sets this bit indicating that the current descriptor has
encountered an error when executing a DMA descriptor that is not otherwise
related to other error bits, e.g., an illegal next descriptor address flagged by the
system address decoder, which the DMA Engine encounters in the current
descriptor after having successfully completed the data transfer for the current
descriptor including any associated completions/interrupts.
®
®
5100 MCH Chipset does not detect unaffiliated errors.
5100 MCH Chipset DMA Engine does not record/detect any soft
Section
Description
3.11.22.2).
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
239