HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 347

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
Table 110.
5.20
Figure 36.
July 2009
Order Number: 318378-005US
Reset Sequences and Durations (Sheet 2 of 2)
SMBus Interfaces Description
The Intel
(SMBus) Specification, Version 2.0 compliant target interfaces. These interfaces are
used to support platform level operations such as Serial Presence Detect for DDR2
DIMMs, PCI Hot Plug*, and configuration of platform devices. Each of these interfaces
have dedicated uses as shown in
Chipset SMBus Interfaces,”
Intel
SMBus SPD0 is dedicated to memory serial presence detect and DDR2 DIMM
configuration. SMBus SPD0 is dedicated to channel 0 and channel 1 DDR2 DIMMs. The
SMBus GPIO is dedicated to PCI Hot Plug* support and is not currently a supported
feature.
Each SMBus interface consists of two interface pins; one a clock, and the other serial
data. Multiple initiator and target devices may be electrically present on the same pair
of signals. Each target recognizes a start signaling semantic, and recognizes its own 7-
bit address to identify pertinent bus traffic. The MCH address is hard-coded to
01100000b (60h).
The SMBus protocol allows for traffic to stop in “mid sentence,” requiring all targets to
tolerate and properly “clean up” in the event of an access sequence that is abandoned
by the initiator prior to normal completion. The MCH is compliant with this requirement.
The protocol comprehends “wait states” on read and write operations, which the MCH
takes advantage of to keep the bus busy during internal configuration space accesses.
RESETI#
deassertion
RESETI#
deassertion
From
®
5100 Memory Controller Hub Chipset SMBus Interfaces
®
®
5100 MCH Chipset provides three fully functional System Management Bus
Hard/Core
deassertion
FSB{0/1}
RESET#
deassertion
5100 MCH Chipset
To
PCI Hot
Plug* only
Slave
DDR2
SPD
4-6 HCLK
1 mS
Duration
and as described in
SPD0 SMBus
GPIO SMBus
CFG SMBus
JTAG
Figure 36, “Intel® 5100 Memory Controller Hub
MCH
MCH
Source
Hub Chipset
Intel® 5100
MCH waits for a common rising edge on all internal
clocks, then releases core reset(s).
MCH enforces delay between RESETI# and FSB{0/
1}RESET# deassertion. ESI handshake is
incremental to the timer.
Controller
Memory
Section 2.4, “SMBus Interfaces.”
Intel
®
5100 Memory Controller Hub Chipset
Comment
0926071438
Datasheet
347