HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 53

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Signal Description—Intel
2.5
Table 19.
2.6
Table 20.
July 2009
Order Number: 318378-005US
Extended Debug Port (XDP) Signal List
Extended Debug Port (XDP) Signals
JTAG Bus Signal List
JTAG Bus Signals
XDPCOMCRES
XDPD[15:0]#
XDPSTBN#
XDPSTBP#
XDPODTCRES
XDPRDY#
XDPSLWCRES
TCK
TDI
TDO
TMS
TRST#
Signal Name
Signal Name
®
5100 MCH Chipset
Analog
Analog
Analog
Type
Type
I/O
I/O
I/O
O
I
I
I
I
XDP Bus Compensation:
Data Bus:
Data Bus Strobe Negative and Positive Phases:
XDP Bus Compensation:
Data Bus Ready:
XDP Bus Slew Rate Compensation:
Test Clock:
TCK provides the JTAG clock input for the MCH Test Bus (also known as the Test
Access Port).
Test Data In:
TDI transfers serial test data into the MCH. TDI provides the serial input needed
for JTAG specification support.
Test Data Out:
TDO transfers serial test data out of the MCH. TDO provides the serial output
needed for JTAG specification support.
Test Mode Select:
TMS is a JTAG specification support signal used by debug tools.
See the Debug Port Design Guide for Intel
Platforms (External Version) for further information.
Test Reset:
TRST# resets the Test Access Port (TAP) logic. TRST# must be driven low
during power on Reset. Asynchronous reset of the JTAG interface.
Description
Description
Intel
®
®
5100 Memory Controller Hub Chipset
5000 Series Chipset Based
Datasheet
53