HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 247

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.11.23.5
July 2009
Order Number: 318378-005US
1. If multiple writes happen to this register when the DMA channel is busy, prior writes will be
2. The erroneous CHANCMD register is first cleared by Software and then the CHANERR.chan_cmd
overwritten and only the last command that remains, when the engine scans the CHANCMD
register, will be serviced if it is valid. The exception to this is the Append DMA command which is
processed after the earlier command is completed.
error register field is reset by Software.
CHANCMD[3:0] - DMA Channel Command Register
This register is written by the controlling process to invoke DMA operation. Setting
more than one of these bits with the same write operation will result in an Fatal error
(affiliated). It is also the responsibility of the software to program the correct DMA
command into this register depending on the operational needs since the DMA Engine
will only process the last written
descriptor. The Start DMA bit will not progress if there any hard/affiliated errors (Fatal)
recorded in the CHANERR register until the software clears
If the Start DMA is set and the CHANERR register is not cleared for affiliated errors,
then the CHANERR.chancmd_error bit will be asserted and the engine will be in halted
status.
Offset:
7:6
5
4
3
2
1
0
Bit
RV
RW
RW
RW
RW
RW
RW
Attr
®
5100 MCH Chipset
214h, 194h, 114h, 94h
0h
0
0
0
0
0
0
Default
Reserved
Rst_DMA: Reset DMA
Set this bit to reset the DMA channel. When this bit has been set, the DMA channel
terminates pending transactions immediately and releases any buffers that have
been allocated. Setting this bit is a last resort to recover the DMA channel from a
programming error or other problem such as deadlocks from cache coherency
protocol, misprogrammed channels or other bottlenecked traffic scenarios that will
help recovery.
Execution of this command does not generate an interrupt or generate status. This
command causes the DMA channel to return to a known state (Halted).
The CDAR register will log the current descriptor address when the Reset DMA is
processed by the DMA Engine. In this mode, only the CHANSTS.DMA_trans_state
register field will be updated to reflect the final state of the DMA Engine.
Res_DMA: Resume DMA
Set this bit to resume DMA transfer after the channel has been suspended. When
this bit has been set, the DMA channel resumes operation by fetching the last
descriptor (pointed to by CDAR defined in
Descriptor Address.
Abrt_DMA: Abort DMA
Set this bit to abort the current DMA transfer. When this bit has been set, the DMA
channel will abort the current DMA transfer if the current DMA transfer is active and
sets DMA Transfer Status as “Halted” in channel status register. Otherwise, it just
sets DMA Transfer Status as “Halted” in channel status register.
Susp_DMA: Suspend DMA
Set this bit to suspend the current DMA transfer. When this bit has been set, the
DMA channel halts at current descriptor boundary, sets DMA Transfer Status as
“Suspended”, and waits for a Resume DMA or Abort DMA command.
Appnd_DMA: Append DMA
Set this bit to append a new descriptor or a chain of descriptors. When this bit has
been set, the DMA channel checks if it is at the last descriptor or finished the last
descriptor. If it is, the DMA channel fetches the last descriptor. If it is not at the last
descriptor, the DMA Engine ignores this bit.
Strt_DMA: Start DMA
Set this bit to initiate a new DMA transfer. When this bit has been set, the DMA
channel begins to fetch a new descriptor at the address of the CHAINADDR register.
The processor or I/O device must update the CHAINADDR register before it sets
this bit.
1
command after it has completed servicing a
Description
Intel
Section
®
2
5100 Memory Controller Hub Chipset
it. (See
3.11.23.7) and following the Next
Section
3.11.23.8.
Datasheet
247