HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 336

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Note:
5.17.4.5
5.17.4.6
Figure 33.
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5100 Memory Controller Hub Chipset
Because of the PCI Express* ordering rules, transactions after an inbound write must
wait until after the write is globally visible. The inbound queue must be deep enough
such that continuous inbound traffic is not stalled waiting for the above write sequence
even under heavily loaded conditions.
For write transactions with the Don’t Snoop attribute, the PCI Express* unit (following
all inbound ordering rules) will simply issue a write command to memory without
snooping the processor buses. Note that ordering is required between normal and
“Don’t Snoop” transactions.
PHOLD Support
The MCH supports the PHOLD protocol. This protocol is used for legacy ISA devices
which did not allow the possibility for being both a master and a slave device
simultaneously. Example devices that use the PHOLD protocol are legacy floppy drives
and parallel port.
Interrupt Handling
A PCI Express* device represents interrupts with either MSI or inbound interrupt
messages (Assert_INTx/Deassert_INTx).
Each PCI Express* port of the MCH is responsible for tracking assert/deassert
messages for each of the four interrupts (INTA, INTB, INTC, INTD) and representing
them with four output virtual (Assert_INTA, Assert_INTB, Assert_INTC, and
Assert_INTD) messages to the ICH9R.
Figure 33, “Legacy Interrupt Routing (INTA Example)”
interrupts are routed to the ICH9R. The example shown represents Interrupt A and this
logic is replicated for the four interrupts. The bits depicted are software visible.
When a PCI Express* assert message is received for a specific interrupt, another assert
message will not arrive until after a deassert message has arrived for that interrupt
first.
When MSI interrupts are used, the MCH treats these writes as any other inbound write.
The difference is that MSI writes are detected as a write to addresses in the range FEE0
0000h - FEDF FFFFh. If the write falls within this range, the MCH issues the write to
both processor buses where it will be claimed by the targeted CPU.
Legacy Interrupt Routing (INTA Example)
Assert/Deassert_INTA
Assert_INTA/Deassert_INTA
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(to ICH9R)
5100 MCH Chipset—Functional Description
illustrates how the PCI Express*
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Order Number: 318378-005US
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July 2009