HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 172

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.12.28
3.8.12.29
3.8.13
Intel
Datasheet
172
®
5100 Memory Controller Hub Chipset
PEX_UNIT_FERR[7:2] - PCI Express* First Unit Error Register
This register records the occurrence of the first unit errors that are specific to this PCI
Express* port caused by external activities, e.g., VPP error due to a malfunctioning port
on the SMBus that did not receive acknowledge due to a PCI Hot Plug* event. The unit
errors are sent to the Coherency Engine to classify as to which port cluster it came from
ports 2-3 or ports 4-7 and the errors are recorded in Coherency Engine and appropriate
interrupts generated through ERR pins.
PEX_UNIT_NERR[7:2] - PCI Express* Next Unit Error Register
This register records the occurrence of subsequent unit errors that are specific to this
PCI Express* port caused by external activities, e.g., VPP error due to a malfunctioning
port on the SMBus that did not receive acknowledge due to a PCI Hot Plug* event. The
next unit errors are sent to the Coherency Engine where the errors are further recorded
and appropriate interrupts are generated through ERR pins.
Error Registers
This section describes the registers that record the first and next errors, logging,
detection masks, signaling masks, and error injection control. The FERR_GLOBAL (first
error register) is used to record the first error condition. The NERR_GLOBAL register is
used to record subsequent errors.
The contents of FERR_GLOBAL and NERR_GLOBAL are “sticky” across a reset (while
PWRGOOD remains asserted). This provides the ability for firmware to perform
diagnostics across reboots. Note that only the contents of FERR_GLOBAL affects the
update of the any error log registers.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
31:1
31:1
Bit
Bit
Bit
0
0
0
RWCST
RWCST
RWCST
Attr
Attr
Attr
RV
RV
7-2, 0
0
160h
2-3, 4-7
0
168h
2-3, 4-7
0
16Ch
Default
Default
Default
0h
0h
0
0
0
Next_NFAT_COR_Err_IO0: PEX - Data Link Layer Protocol Error
(uncorrectable)
Reserved
First_FAT_VPP_Err: VPP Error for PCI Express* port
Records the occurrence of the first VPP error if this bit is not set prior.
Software clears this when the error has been serviced.
Reserved
Next_FAT_VPP_Err: VPP Error for PCI Express* port
Records the occurrence of subsequent VPP errors after the
PEX_UNIT_FERR.First_FAT_VP_ERR is set.
Software clears this when the error has been serviced.
Intel
®
5100 MCH Chipset—Register Description
Description
Description
Description
Order Number: 318378-005US
July 2009