HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 327

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.16.3
Note:
5.16.3.1
July 2009
Order Number: 318378-005US
first half of the buffer to the last half). This must be done without setting the ‘no snoop’
control bits.
For hot removal, the client must release DMA Engine resources.
To release DMA resources, the client makes sure DMA operation is halted or aborts DMA
operation. The client relinquishes control via the DMA Engine driver.
Interrupt Handling
Interrupt handling is very OS specific. This section illustrates how DMA Engine facilities
are architected to be used by explaining how the various software entities can use DMA
Engine facilities to process interrupts. Refer to the DMA Engine Driver specification for
OS specific details and implementation requirements. Thus, this section serves as a
guide for the DMA Engine Driver specification.
The DMA Engine driver provides a DMA Engine Interrupt Service Routine (ISR) that is
dispatched when the DMA Engine device generates an interrupt. The ISR disables
interrupts from the DMA Engine device and dispatches the DMA Engine Interrupt
Handler, which calls one or more Channel Interrupt Callbacks to process the interrupt.
When all interrupt conditions have been processed, interrupts are re-enabled.
For a client I/O device driver to use DMA Engine interrupts, it must register its “Channel
Interrupt Callback” with the DMA Engine Driver and then enable interrupts by setting
the “Interrupt upon the completion of this descriptor” bit in the Descriptor Control Field
of descriptors for which it wants completion interrupts and may optionally set the “Error
Interrupt Enable” in the CHANCTRL register.
The DMA Engine driver sets the Master Interrupt Enable bit in the INTRCTRL register to
enable interrupts.
The DMA Engine ISR is invoked when any channel generates an interrupt. The ISR
dispatches the DMA Engine interrupt handler that determines which channels are
generating a Channel Attention and for each channel requiring attention, calls that
channel’s interrupt handler.
The ISR reads the Attention Status register to determine which channels generated an
interrupt (the read resets the Attention Status register). When a DMA channel
generates an interrupt, the chipset sets the appropriate bit in the ATTNSTATUS register
and sets the Interrupt Disable bit in the CHANCTRL register. This inhibits that channel
from generating another interrupt until the software clears the “Interrupt Disable” bit in
the CHANCTRL register. Interrupt events that occur while Interrupt Disable is set are
remembered and might cause an interrupt after Interrupt Disable is reset.
Interrupt Service Routine (ISR)
The ISR reads the INTRCTRL register to validate that there is an interrupt that needs
service. Reading the INTRCTRL resets the Master Interrupt Enable, which disables the
interrupt generation and clears the Interrupt bit. In a multiprocessor system, this
allows the first CPU that reads the INTRCTRL after an interrupt to read the Interrupt bit
set and ISRs on ISR instances on other CPUs will read the bit reset and know that
another instance of the ISR is processing interrupts.
• If the ISR reads the INTRCTRL register and the Master Interrupt Enable is not set,
• If the ISR reads the INTRCTRL register and Master Interrupt Enable is set, but
This indicates that another CPU’s ISR is processing the interrupt. In this case, the
ISR simply returns without dispatching the DMA Engine Interrupt Handler.
Interrupt Status is not, this indicates either a spurious interrupt or that another
device is sharing the interrupt level. In either case, the ISR re-enables interrupts
®
5100 MCH Chipset
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
327