HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 195

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
Table 65.
3.9.4
July 2009
Order Number: 318378-005US
Host to MEM Gear Ratio Mux Select
DRAM Timing Registers
The DRTA and DRTB registers defines timing parameters that work with the DDR2
DRAMs in the appropriate channel. The parameters for these devices can be obtained
by serial presence detect. This register must be set to provide timings that satisfy the
specifications of all SDRAM’s detected. For example, if SDRAM’s present have different
TRCs, the maximum should be used to program this register. Consult the appropriate
JEDEC DDR2 SDRAM specifications for the technology of the devices in use.
Devices are usually presented as 4-4-4, 5-5-5, etc. These numbers indicate T
and T
minimum values):
T
T
T
T
command
In the calculations in the text below, “T” is used to denote a time in ns while “n” refers
to the number of clock cycles. So, for example:
The actual register filed names are always T
clock cycles). BL, the burst length, is always set to eight (four clock cycles) for Intel
5100 MCH Chipset.
Most of the bit fields represent timing rules that define a minimum separation of events
that will be enforced by the device. Transactions that would break one of the timing
rules (if issued to the DIMMs) are deemed to be “in conflict” and will not be issued.
FSB: Memory Frequency
CAC
RCD
RP
RAS
• T
• N
: Precharge time (minimum time required to precharge a row)
/T
: Minimum/Maximum time a row can be active before it receives a precharge
: RAS to CAS delay (minimum delay between RAS and CAS strobes).
FAW
RP
FAW
CL
333:333
267:267
333:267
267:333
with a fourth optional parameter, T
: Column access time (minimum time between CAS strobe and data access)
®
refers to 37.5 ns
refers to 10 cycles (@ 266 MHz)
5100 MCH Chipset
Gear Ratio
1:1
5:4
4:5
RAS
FAW
(which has both maximum and
(though delays are programmed in
conservative
conservative
Option
Intel
only
®
5100 Memory Controller Hub Chipset
00000000h
00001020h
00040000h
Value
CAC
Datasheet
, T
RCD
®
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