HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 314

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.13.5.1
5.13.5.2
5.13.5.3
Figure 29.
Intel
Datasheet
314
®
5100 Memory Controller Hub Chipset
PCI Express* Training
To establish a connection between PCI Express* endpoints, they both participate in a
sequence of steps known as training. This sequence will establish the operational width
of the link as well as adjust skews of the various lanes within a link so that the data
sample points can correctly take a data sample off of the link. In the case of a x8 port,
the x4 link pairs will first attempt to train independently, and will collapse to a single
link at the x8 width upon detection of a single device returning link ID information
upstream. Once the number of links has been established, they will negotiate to train
at the highest common width, and will step down in its supported link widths in order to
succeed in training. The ultimate result may be that the link has trained as a x1 link.
Although the bandwidth of this link size is substantially lower than a x8 link or x4 link,
it will allow communication between the two devices. Software will then be able to
interrogate the device at the other end of the link to determine why it failed to train at
a higher width.
8b/10b Encoder/Decoder and Framing
As a transmitter, the physical layer is responsible for encoding each byte into a 10-bit
data symbol before transmission across the link. Packet framing is accomplished by the
physical layer by adding special framing symbols (STP, SDP, END). PCI Express*
implements the standard Ethernet and InfiniBand* 8b/10b encoding mechanism.
Elastic Buffers
Every PCI Express* port implements an independent elastic buffer for each PCI
Express* lane. The elastic buffers are required since the Intel
PCI Express* endpoints could be clocked from different sources. Clocks from different
sources will never be exactly the same. The outputs of the elastic buffers feed into the
deskew buffer.
PCI Express* Elastic Buffer (x4 Example)
Remote Clock = 2.499 GHz
Local Clock = 2.501 GHz
Intel
®
5100 MCH Chipset—Functional Description
®
Order Number: 318378-005US
5100 MCH Chipset and
July 2009