HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 163

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.12.11
3.8.12.12
3.8.12.13
July 2009
Order Number: 318378-005US
HDRLOG0[7:2,0] - Header Log 0
This register contains the first 32 bits of the header log locked down when the first
uncorrectable error occurs. Headers of the subsequent errors are not logged.
HDRLOG1[7:2,0] - Header Log 1
This register contains the second 32 bits of the header log.
HDRLOG2[7:2,0] - Header Log 2
This register contains the third 32 bits of the header log.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
31:9
31:0
31:0
31:0
4:0
Bit
Bit
Bit
Bit
8
7
6
5
®
ROST
ROST
ROST
ROST
Attr
Attr
Attr
Attr
RO
RO
RO
RO
RV
5100 MCH Chipset
7-2, 0
0
118h
7-2, 0
0
11Ch
7-2, 0
0
120h
7-2, 0
0
124h
Default
Default
Default
Default
0h
0h
0h
0h
0h
0
0
0
0
Reserved
ECRCCHKEN: ECRC Check Enable
This bit when set enables ECRC checking.
ECRCCHKCAP: ECRC Check Capable
The Intel
ECRCGENEN: ECRC Generation Enable
The Intel
ECRCGENCAP: ECRC Generation Capable
The Intel
FERRPTR: First error pointer
The First Error Pointer is a read-only register that identifies the bit position
of the first error reported in the Uncorrectable Error status register. Left
most error bit if multiple bits occurred simultaneously.
HDRLOGDW0: Header of TLP (DWORD 0) associated with first
uncorrectable error
HDRLOGDW2: Header of TLP (DWORD 2) associated with error
HDRLOGDW1: Header of TLP (DWORD 1) associated with error
®
®
®
5100 MCH Chipset does not support ECRC.
5100 MCH Chipset does not generate ECRC.
5100 MCH Chipset does not generate ECRC.
Description
Description
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
163