HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 159

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.12.4
3.8.12.5
July 2009
Order Number: 318378-005US
UNCERRMSK[7:2] - Uncorrectable Error Mask
This register masks uncorrectable errors from the UNCERRSTS[2:7] register from being
signaled.
UNCERRMSK[0] - Uncorrectable Error Mask For ESI Port
This register masks uncorrectable errors from the UNCERRSTS[0] register (ESI port)
from being signaled.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
31:21
31:22
11:6
3:1
3:1
Bit
Bit
Bit
20
19
18
17
16
15
14
13
12
21
0
5
4
0
®
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWCST
Attr
Attr
5100 MCH Chipset
Attr
RV
RV
RV
RV
RV
RV
0
0
104h
7-2
0
108h
0
0
108h
Default
Default
Default
000
0h
0h
0h
0
0
0
0
0
0
0
0
0
0
0
0
0
0h
0
Reserved
IO2Msk: Received an Unsupported Request
Reserved
IO9Msk: Malformed TLP Status
IO10Msk: Receiver Buffer Overflow Mask
IO8Msk: Unexpected Completion Mask
IO7Msk: Completer Abort Status
IO6Msk: Completion Timeout Mask
IO5Msk: Flow Control Protocol Error Mask
IO4Msk: Poisoned TLP Mask
Reserved
IO19Msk: Surprise Link-down Error Mask
IO0Msk: Data Link Layer Protocol Error Mask
Reserved
IO3Msk:Training Error Mask
Note:
Reserved
IO18Msk: ESI Reset timeout
Reserved
IO3Err:Training Error Status
Note:
This field should not be used for setting Training error Mask due to
a recent PCI Express* Base Specification, Rev. 1.0a Errata Dec
2003 to remove training error. Hardware behavior is undefined.
This field should not be used for obtaining Training error status
due to a recent PCI Express* Base Specification, Rev. 1.0a Errata
Dec 2003 to remove training error. Hardware behavior is
undefined.
Description
Description
Intel
Description
®
5100 Memory Controller Hub Chipset
Datasheet
159