HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 4

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Intel
Datasheet
4
®
5100 Memory Controller Hub Chipset
3.6
3.7
3.8
Intel
Detailed Configuration Space Maps.......................................................................76
Register Definitions ............................................................................................92
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
3.8.7
3.8.8
®
5100 Memory Controller Hub Chipset Fixed Memory Mapped Registers ............74
PCI Standard Registers............................................................................92
3.8.1.1
3.8.1.2
3.8.1.3
3.8.1.4
3.8.1.5
3.8.1.6
SID - Subsystem Identity ........................................................................97
Address Mapping Registers ......................................................................97
3.8.3.1
3.8.3.2
3.8.3.3
3.8.3.4
3.8.3.5
3.8.3.6
3.8.3.7
3.8.3.8
3.8.3.9
3.8.3.10 EXSMRTOP - Extended System Management RAM Top Register ..... 103
3.8.3.11 EXSMRAMC - Expansion System Management RAM Control Register ....
3.8.3.12 HECBASE - PCI Express* Extended Configuration Base Address Register
Interrupt Redirection Registers ............................................................... 104
3.8.4.1
3.8.4.2
Boot and Reset Registers ....................................................................... 105
3.8.5.1
3.8.5.2
3.8.5.3
3.8.5.4
3.8.5.5
3.8.5.6
Control and Interrupt Registers .............................................................. 108
3.8.6.1
3.8.6.2
3.8.6.3
3.8.6.4
PCI Express* Device Configuration Registers ............................................ 110
PCI Express* Header............................................................................. 112
3.8.8.1
3.8.8.2
3.8.8.3
3.8.8.4
3.8.8.5
3.8.8.6
3.8.8.7
3.8.8.8
3.8.8.9
3.8.8.10 SBUSN[7:2] - Secondary Bus Number........................................ 117
3.8.8.11 SUBUSN[7:2] - Subordinate Bus Number ................................... 117
3.8.8.12 SEC_LT[7:2] - Secondary Latency Timer .................................... 118
3.8.8.13 IOBASE[7:2] - I/O Base Register............................................... 118
3.8.8.14 IOLIM[7:2] - I/O Limit Register ................................................. 118
3.8.8.15 SECSTS[7:2] - Secondary Status............................................... 119
VID - Vendor Identification Register .............................................93
DID - Device Identification Register .............................................93
RID - Revision Identification Register ...........................................93
CCR - Class Code Register ..........................................................95
HDR - Header Type Register .......................................................96
SVID - Subsystem Vendor Identification Register...........................96
PAM0 - Programmable Attribute Map Register 0.............................98
PAM1 - Programmable Attribute Map Register 1.............................98
PAM2 - Programmable Attribute Map Register 2.............................99
PAM3 - Programmable Attribute Map Register 3.............................99
PAM4 - Programmable Attribute Map Registers 4 ......................... 100
PAM5 - Programmable Attribute Map Register 5........................... 101
PAM6 - Programmable Attribute Map Register 6........................... 101
SMRAMC - System Management RAM Control Register ................. 102
EXSMRC - Extended System Management RAM Control Register .... 102
104
104
REDIRCTL - Redirection Control Register .................................... 104
REDIRBUCKETS - Redirection Bucket Number Register ................. 105
SYRE - System Reset Register................................................... 105
CPURSTCAPTMR: CPU Reset Done Cap Latency Timer .................. 106
POC - Power-On Configuration Register ...................................... 107
SPAD[3:0] - Scratch Pad Registers ............................................ 108
SPADS[3:0] - Sticky Scratch Pad............................................... 108
BOFL[3:0] - Boot Flag Register ................................................. 108
PROCENABLE: Processor Enable Global Control............................ 108
FSBC1: Processor Bus Controller ............................................... 109
FSBS[1:0] - Processor Bus Status Register ................................. 109
XTPR[15:0] - External Task Priority Register ............................... 109
PEXCMD[7:2,0]- Command Register .......................................... 113
PEXSTS[7:2,0] - Status Register ............................................... 114
CLS[7:2,0] - Cache Line Size .................................................... 116
PRI_LT[7:2,0] - Primary Latency Timer ...................................... 116
BIST[7:2,0] - Built-In Self-test ................................................. 116
BAR0[7:2,0] - Base Address Register 0 ...................................... 116
BAR1[7:2,0] - Base Address Register 1 ...................................... 116
EXP_ROM[0]: Expansion ROM Registers ..................................... 117
PBUSN[7:2] - Primary Bus Number............................................ 117
Intel
®
5100 MCH Chipset—Contents
Order Number: 318378-005US
July 2009