HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 282

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.2.3.2
Table 88.
5.2.4
5.2.4.1
Intel
Datasheet
282
®
5100 Memory Controller Hub Chipset
Memory Technology
SDRAM Signal Allocations for Different Technologies
Memory RAS
The Intel
Rank Sparing, Patrol and Demand Scrubbing, ECC and SDDC, a memory location can
be poisoned. Memory mirroring is not a supported feature on the Intel
Chipset.
Memory Sparing
At configuration time, a DIMM rank is set aside to replace a defective DIMM rank. Each
channel can allow a single rank to be designated as spare by enabling rank sparing,
setting SPCPC.SPAREN and designating the spare rank with the SPCPC.SPRANK bits.
The spare rank must not be allocated in the DMIR registers.
When the correctable error rate for a failing DIMM rank reaches a pre-determined
threshold (CERRCNT, SPCPS.LBTHR), an interrupt is issued to initiate a spare copy
which copies the contents of the failed rank to the spare. While the copy engine is
automatically reading locations from the failing DIMM rank and writing them to the
spare (see
“SPCPS[1:0]: Spare Copy
rank, and system writes will be written to both the failing DIMM rank and the spare
DIMM rank. During the spare copy operation, the Memory Controller (MC) allocates
approximately 20% of bandwidth to operations to read from the failed rank and write to
the spare. At the completion of the copy, the failing DIMM rank is disabled and the
spare DIMM rank will be used in its place. The MCH will change the rank numbers in the
DMIRs from the failing rank to the spare rank. DMIR.LIMITs are not updated.
Spare copy operation initiation and completion generate error messages (M20/M21)
which can be used by software to note the failed rank etc. Patrol scrubbing is
suspended during a spare copy operation.
Sparing occurs under the control of the CERRCNT register which maintains a running
count of correctable errors for each rank. This counter uses a leaky bucket algorithm
(SPCPS.LBTHR) to compensate for the anticipated level of correctable errors. Should
the counter (for any one rank) reach the threshold value specified in SPCPC.SETH the
spare copy operation is initiated for the failed rank. Only one rank can be spared so
further sparing is disabled at that point.
The spare rank may be equal or larger than the failed rank, but not smaller. Using a
smaller capacity rank to spare for a larger capacity rank is illegal and will result in
undetermined behavior.
Technology
256 Mb
512 Mb
1 Gb
2 Gb
®
5100 MCH Chipset has many memory RAS features. In conjunction with
Section 3.9.7.1, “SPCPC[1:0]: Spare Copy Control”
Organization
4x16Mx4
4x16Mx8
4x32Mx4
8x16Mx8
8x32Mx4
8x32Mx8
8x64Mx4
4x8Mx8
Status”), system reads will be serviced from the failing DIMM
SDRAM Row bits
RA12-RA0
RA13-RA0
RA14-RA0
Intel
SDRAM Column lines
®
CA11, CA9-CA0
CA11, CA9-CA0
CA11, CA9-CA0
CA11, CA9-CA0
5100 MCH Chipset—Functional Description
CA9-CA0
CA9-CA0
CA9-CA0
CA9-CA0
and
Order Number: 318378-005US
SDRAM Bank lines
Section 3.9.7.2,
®
B1-B0
B2-B0
5100 MCH
July 2009