HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 329

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.17
Note:
July 2009
Order Number: 318378-005US
Interrupt Callback clears the Interrupt Disable bit, it may re-read the CHANSTS and
CHANERR to see if any new interrupt events occurred between the time it last read
them and it set the Interrupt Disable bit.
Note that steps
last read of the CHANSTS register will generate another interrupt (see
“Interrupt
write memory location rather than the CHANSTS register. By not reading the CHANSTS
register, any interrupt event that occurs after the one that generated the interrupt, will
cause another interrupt to be generated after the handler resets Interrupt Disable.
Otherwise, any interrupt event that occurs after the last read of the CHANSTS will
cause another interrupt to be generated.
DMA Engine Driver
This section serves as a guide for the DMA Engine Driver specification and describes the
tasks of the DMA Engine driver with respect to how the DMA Engine driver interfaces
with the chipset. Refer to the DMA Engine Driver specification for specific details and
implementation requirements.
The DMA Engine device appears as a normal PCI Express* device and thus the OS will
load the DMA Engine driver by matching the Vendor and Product information in the PCI
configuration registers of the DMA Engine device.
The DMA registers are at a fixed offset from CB_BAR. The per-port registers are located
via the
of per port registers. These registers form a linked list with the
“NXTPPRSET2 - Next Per Port Register Set”
3.12.0.2, “NXTPPRSET3 - Next Per Port Register Set”
the last register set, which has a value of zero. Thus the driver walks the chain to locate
all of the ports with DMA Engine resources.
The DMA Engine driver is responsible for supplying the DMA Engine ISR and DMA
Engine Interrupt Handler (see
1. Read the Channel Status (CHANSTS) register to determine the current descriptor
2. Process completions for all previous descriptors (implied good status).
3. Process current descriptor.
4. Write CHANCTRL to clear Interrupt Disable.
5. Read the Channel Status (CHANSTS) register to determine if additional descriptors
6. Read the Channel Error (CHANERR) register to determine if additional errors have
7. Return.
and its status.
a.
b. If not good status, perform error processing and reset error bits in CHANERR
have completed.
a.
b. If same descriptor, continue with next step.
occurred.
a.
b. If no errors, continue with next step.
Section 3.11.22.3, “INTRCTRL - Interrupt Control”
If good status, process completion.
register.
If not same descriptor as previous CHANSTS value, go to step
If errors, perform error processing and reset error bits in CHANERR register.
Handling”). Additionally, the handler may choose to read the completion
®
5100 MCH Chipset
5.
and
6.
are optional since any interrupt event that occurs after the
Section 5.16.3.1, “Interrupt Service Routine
pointing to the next register set and
Intel
pointing to the next register set,
®
which points to the first set
5100 Memory Controller Hub Chipset
Section 3.12.0.1,
2.
Section 5.16.3,
and repeat.
(ISR)”).
Section
Datasheet
329