HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 47

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Signal Description—Intel
Table 8.
July 2009
Order Number: 318378-005US
DDR2 Channel 1 Signals (Sheet 2 of 3)
CH1_DQSN[17:0]
CH1_DCLKN[2:0]
CH1_DQSP[17:0]
CH1_DCLKP[2:0]
CH1_DCLKN[3]
CH1_DCLKP[3]
CH1_CS[5:4]#
CH1_CS[3:0]#
CH1_DQ[63:0]
CH1_DRVCRES
CH1_CRESRET
/CH1_CS[5]#
/CH1_CS[4]#
CH1_CRES1
CH1_CRES2
Name
®
5100 MCH Chipset
Type
I/O
I/O
I/O
O
O
O
O
O
O
I
I
I
Memory Channel 1 DDR Clock Negative (Clock 3)/Chip Select (Bit 5):
When 48GB_Mode is strapped High, the signal functions as CH1_CS[5]#. This
is to enable chip select signal to the sixth rank on channel 1.
When 48GB_Mode is strapped Low, the signal functions as CH1_DCLKN[3], the
negative polarity of fourth DRAM Clock on channel 1 (Registered DIMMs, no
unbuffered).
Memory Channel 1 DDR Clock Negative (Clocks 2:0):
Negative polarity of DRAM Clock (Registered DIMMs, no unbuffered). The first
three clocks.
Memory Channel 1 DDR Clock Negative (Clock 3)/Chip Select (Bit 4):
When 48GB_Mode is strapped High, the signal functions as CH1_CS[4]#. This
is to enable chip select signal to the fifth rank on channel 1.
When 48GB_Mode is strapped Low, the signal functions as CH1_DCLKP[3], the
positive polarity of fourth DRAM Clock on channel 1 (Registered DIMMs, no
unbuffered).
Memory Channel 1 DDR Clock Positive (Clocks 2:0):
Positive polarity of DRAM Clock (Registered DIMMs, no unbuffered). The first
three clocks.
Memory Channel 1 DDR2 resistive compensation I/Os:
The DDR circuits generate the logic reference used by inbound receivers by
using CH1_CRES1 and CH1_CRES2. The CH1_CRES2 connects to the same
power supply that is used by the DRAM drivers while CH1_CRES1 is connected
to the board ground. By using an internal divider network, various required
reference points can be generated.
Memory Channel 1 Compensation Reference Return VSS:
Internal ground reference for the impedance and slew rate reference resistors.
Memory Channel 1 Chip Select:
When 48GB_Mode is strapped High, these signals in addition to CH1_CS[3:0]#
specify the SDRAM command in combination with CH1_CAS#, CH1_RAS# and
CH1_WE#. CH1_CS[5:0]# select one of six possible ranks, where CH1_CS[0]#
selects the first rank and CH1_CS[5]# selects the sixth rank.
When 48GB_Mode is strapped Low, these signals function as CH1_DCLKN[3]
and CH1_DCLKP[15], respectively.
Memory Channel 1 Chip Select:
When 48GB_Mode is strapped High, these signals in addition to CH1_CS[5:4]#
specify the SDRAM command in combination with CH1_CAS#, CH1_RAS# and
CH1_WE#. CH1_CS[5:0]# select one of six possible ranks, where CH1_CS[0]#
selects the first rank and CH1_CS[5]# selects the sixth rank.
When 48GB_Mode is strapped Low, the signals specify the SDRAM command in
combination with CH1_CAS#, CH1_RAS# and CH1_WE#. Selects one of four
possible ranks, where CH1_CS[0]# selects the first rank and CH1_CS[3]#
selects the fourth rank.
Memory Channel 1 Data Bus:
64-bit data bus
Memory Channel 1 Data Strobe Negative:
Negative polarity of Strove. Strobe for correction bits, CH1_CB[7:0], and data
bus, CH1_DQ[63:0]. Each nibble of the 64-bit data bus and 8-bit check bit bus
are associated with a strobe signal for a total of 18 strobe signals.
Memory Channel 1 Data Strobe Positive:
Positive polarity of Strove. Strobe for correction bits, CH1_CB[7:0], and data
bus, CH1_DQ[63:0]. Each nibble of the 64-bit data bus and 8-bit check bit bus
are associated with a strobe signal for a total of 18 strobe signals.
Memory Channel 1 Driver Impedance Compensation Resistor:
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
47