HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 194

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 63.
3.9.3.6
Table 64.
3.9.3.7
Intel
Datasheet
194
®
5100 Memory Controller Hub Chipset
MEM to Host Gear Ratio Mux
HOSTTOMEMGRCFG0: Host to MEM Gear Ratio Configuration 0
This register consists of 8 nibbles of mux select data for the proper selection of gearing
behavior on the Host to MC path (south bound).
Host to MEM Gear Ratio Mux Select
HOSTTOMEMGRCFG1: Host to MEM Gear Ratio Configuration 1
This register consists of 8 nibbles of mux select data for the proper selection of gearing
behavior on the Host to MC path (south bound).
Device:
Function:
Offset:
Device:
Function:
Offset:
FSB: Memory Frequency
FSB: Memory Frequency
31:0
31:0
Bit
Bit
333:333
267:267
333:267
267:333
333:333
267:267
333:267
267:333
RWST
RWST
Attr
Attr
16
1
170h
16
1
174h
11111111h
00000000h
Default
Default
HSTMEMGRMUX: Host to MEM Clock Gearing mux selector.
Eight nibbles of mux select for FSB/core to memory/DDR2 geared clock
boundary crossing phase enables.
Refer to
details.
HSTMEMGRMUX: Host to MEM Clock Gearing mux selector.
Eight nibbles of mux select for FSB/core to memory/DDR2 geared clock
boundary crossing phase enables.
Refer to
details.
Gear Ratio
Gear Ratio
1:1
5:4
4:5
1:1
5:4
4:5
Table 64, “Host to MEM Gear Ratio Mux Select”
Table 65, “Host to MEM Gear Ratio Mux Select”
for MEMNDGRCFG1
Intel
conservative
conservative
conservative
conservative
®
Description
Description
5100 MCH Chipset—Register Description
Option
Option
only
only
Order Number: 318378-005US
for the programming
for the programming
00000000h
00002000h
00000406h
11111111h
00005430h
00010320h
Value
Value
July 2009