HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 316

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 97.
5.13.5.6
Intel
Datasheet
316
PEWIDTH[
others
Notes:
1.
2.
3:0]
0000
0001
0010
0011
0100
1000
1001
1010
1011
1100
®
5100 Memory Controller Hub Chipset
Port 0 (ESI) lane reversal is not supported, i.e., only 1 mode (normal x4).
The x2 lane reversal is not supported in any configuration.
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
x8
(0..7, 0..3, 0, 7..0, 7:4, 7)
x8
(0..7, 0..3, 0, 7..0, 7:4, 7)
x8
(0..7, 0..3, 0, 7..0, 7:4, 7)
x8
(0..7, 0..3, 0, 7..0, 7:4, 7)
x8
(0..7, 0..3, 0, 7..0, 7:4, 7)
be established using lane 0 through lane 3 of the MCH and lane 0 through lane 3 of the
link partner. If the connection does not support the x4 link, a x1 link may be
established using lane 0 from the MCH and lane 0 from the link partner.
As an example of lane reversal, when Port 4 through Port 7 are configured as a x16
port, lane 0 through lane 15 of the MCH can be connected to lane 15 through lane 0 of
the PCI Express* connector or PCI Express* link partner. If the connection does not
support the x16 link, a x8 link may be established using lane 0 through lane 7 of the
MCH and lane 15 through lane 8 of the link partner. If the connection does not support
the x8 link, a x4 link may be established using lane 0 through lane 3 of the MCH and
lane 15 through lane 12 of the link partner. If the connection does not support the x4
link, a x1 link may be established using lane 0 from the MCH and lane 15 from the link
partner.
The key to remembering which port combinations are allowed to be combined for any
particular lane width, the control port is always required to be one of the ports used in
order to negotiate the link state, the lanes must consist of consecutive x1, x4 or x8
ports in the allowed combinations. In the case of the above x16 lanes, port 4 is the
control port. Any lesser lane width x8, x4 or x1 must utilize port 4 to establish a valid
link.
Intel
Polarity Inversion
The PCI Express* Base Specification, Rev. 1.0a defines a concept called polarity
inversion. Polarity inversion allows the board designer to connect the D+ and D- lines
incorrectly between devices. The Intel
Port 2
®
5100 Memory Controller Hub Chipset Lane Reversal Matrix
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
Port 3
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
x8
(0..7, 0..3, 0, 7..0, 7:4, 7)
x8
(0..7, 0..3, 0, 7..0, 7:4, 7)
x16
(0..15, 0..7, 0..3, 0, 15..0, 15..8, 15:12, 15)
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
x8
(0..7, 0..3, 0, 7..0, 7:4, 7)
x8
(0..7, 0..3, 0, 7..0, 7:4, 7)
x16
(0..15, 0..7, 0..3, 0, 15..0, 15..8, 15:12, 15)
Port 4
®
5100 MCH Chipset supports polarity inversion.
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
Intel
Port 5
®
5100 MCH Chipset—Functional Description
x4
(0..3), 0, (3..0), 3
x8
(0..7, 0..3, 0, 7..0, 7:4, 7)
x4
(0..3), 0, (3..0), 3
x8
(0..7, 0..3, 0, 7..0, 7:4, 7)
x4
(0..3), 0, (3..0), 3
x8
(0..7, 0..3, 0, 7..0, 7:4, 7)
x4
(0..3), 0, (3..0), 3
x8
(0..7, 0..3, 0, 7..0, 7:4, 7)
Port 6
Order Number: 318378-005US
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
x4
(0..3), 0, (3..0), 3
Port 7
July 2009