HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 44

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

2.2
2.2.1
Table 7.
Intel
Datasheet
44
®
5100 Memory Controller Hub Chipset
DDR2 Memory Channels
DDR2 Channel 0
DDR2 Channel 0 contains the following signals.
DDR2 Channel 0 Signals (Sheet 1 of 3)
CH0_DCLKN[2:0]
CH0_DCLKN[3]
CH0_CKE[2:0]
/CH0_ODT[4]
/CH0_ODT[5]
/CH0_CS[5]#
CH0_A[14:0]
CH0_BA[2:0]
CH0_CB[7:0]
CH0_CKE[3]
CH0_A[15]
CH0_CAS#
Name
Type
I/O
O
O
O
O
O
O
O
O
Memory Channel 0 Address bus (Bit 15)/On Die Termination (Bit 4):
When 48GB_Mode is strapped High, the signal functions as CH0_ODT[4]. This
is to enable on die termination signal to the fifth rank on channel 0.
When 48GB_Mode is strapped Low, the signal functions as CH0_A[15] which
provides multiplexed row and column address to SDRAM as the sixteenth
Address bit on channel 0.
Memory Channel 0 Address bus (Address Bits 14:0):
Provides multiplexed row and column address to SDRAM.
Memory Channel 0 Bank Address:
Selects the bank within a rank, up to eight each.
Memory Channel 0 Column Address Strobe:
Used in write and pre-charge operations of DRAM. Specifies the SDRAM
command in combination with CH0_CS#, CH0_RAS# and CH0_WE#.
Memory Channel 0 Correction Bits:
Eight bits used for ECC calculations across channel 0.
Memory Channel 0 Clock Enable (Bit 3)/On Die Termination (Bit 5):
When 48GB_Mode is strapped High, the signal functions as CH0_ODT[5]. This
is to enable on die termination signal to the sixth rank on channel 0. In
48GB_Mode, there is only one Clock Enable required for each of the three
DIMM slots required for channel 0.
When 48GB_Mode is strapped Low, the signal functions as CH0_CKE[3], a
command register enable per rank of a possible four ranks per channel, where
CH0_CKE[0] is for the first rank and CH0_CKE[3] is for the fourth rank on
channel 0.
Memory Channel 0 Clock Enable (Bits 2:0) :
When 48GB_Mode is strapped High, signals function as command register
enables per DIMM for each of the required 3 DIMM slots on channel 0, where
CH0_CKE[0] is for the first DIMM slot and CH0_CKE[2] is for the third DIMM
slot. The first DIMM slot is furthest from the MCH.
When 48GB_Mode is strapped Low, signals function as command register
enable per rank of a possible four ranks per channel, where CH0_CKE[0] is for
the first rank and CH0_CKE[3] is for the fourth rank. The first rank is in the first
DIMM slot which is the furthest DIMM slot from the MCH.
Refer to the Quad-Core and Dual-Core Intel
with Intel
Embedded, and Storage Applications – Platform Design Guide or Intel
Duo Processors T9400 and SL9400 and Intel
Chipset for Communications and Embedded Applications – Platform Design
Guide for more details.
Memory Channel 0 DDR Clock Negative (Clock 3)/Chip Select (Bit 5):
When 48GB_Mode is strapped High, the signal functions as CH0_CS[5]#. This
is to enable chip select signal to the sixth rank on channel 0.
When 48GB_Mode is strapped Low, the signal functions as CH0_DCLKN[3], the
negative polarity of fourth DRAM Clock on channel 0 (Registered DIMMs, no
unbuffered).
Memory Channel 0 DDR Clock Negative (Clocks 2:0):
Negative polarity of DRAM Clock (Registered DIMMs, no unbuffered). The first
three clocks.
®
5100 Memory Controller Hub Chipset for Communications,
Intel
Description
®
5100 MCH Chipset—Signal Description
®
®
Xeon
5100 Memory Controller Hub
Order Number: 318378-005US
®
Processor 5000 Sequence
®
Core™2
July 2009