HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 210

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 69.
3.9.8.2
Note:
Note:
3.9.8.3
Intel
Datasheet
210
®
5100 Memory Controller Hub Chipset
The table below lists some recommended settings for the RANKTHRESHOLD registers.
This assumes a soft error rate (EER) of 1 error per week per GB of installed memory.
The drip rate is divided by two for conservatism (this means a rank getting over half
the EER will have a CERRCNT that increments). The assumed value of ERRPER is the
369AC9FFh to give a scaling of 10
RANKTHRESHOLD Recommended Settings
1: EER - Expected Error Rate: Expected Number of Soft Errors / Week
2: EEP - Expected Error Period (= 1/EER): Number of hours between errors
3: Counter saturated - use max value (or higher prescaler value).
CERRCNT[1:0]: Correctable Error Count
These registers implement the “leaky-bucket” counters for correctable errors for each
rank. Each field “limits” at a value of “255” (“1111 1111”). Non-zero counts are
decremented when the RANKTHRESHOLD threshold is reached by the error period
counter. Counts are frozen at the threshold defined by SPCPC.SETH and set the
SPCPS.LBTHR bit. Writing a value of “1111 1111” clears and thaws the count. Changing
SPCPC.SETH will thaw the count, but will not clear it.
This register counts the number of correctable errors based on code word granularity.
Since each 32 bytes of a cache line plus 4 bytes of ECC constitute a code word, the
correctable errors are incremented if the ECC check indicates an correctable error.
Thus, there can be up to 2 correctable errors per cache line if both portions were
deemed correctable.
Aliased uncorrectable errors are not counted as correctable errors.
This register “works” whether or not sparing is enabled.
CERRCNT_EXT[1:0]: Correctable Error Count
Extension of CERRCNT register for ranks 4 and 5.
Device:
Function:
Offset:
31:24
23:16
15:8
Rank Size
7:0
Bit
512 MB
256 MB
8 GB
4 GB
2 GB
1 GB
RWCST
RWCST
RWCST
RWCST
Attr
22, 21
0
180h
EER
0.25
Default
0.5
8
4
2
1
0h
0h
0h
0h
1
RANK3: Error Count for Rank 3
RANK2: Error Count for Rank 2
RANK1: Error Count for Rank 1
RANK0: Error Count for Rank 0
EEP
168
336
672
21
42
84
2
Drip Rate
9
(2xEEP)
(converts ns to seconds).
1344
168
336
672
42
84
ERRPER
Intel
Setting
10
10
10
10
10
10
Description
9
9
9
9
9
9
®
5100 MCH Chipset—Register Description
266 MHz
Setting based on 2xEEP
FFFFh
13B0h
2760h
4EC0h
9D80h
9D8h
RANKTHRESHOLD
Order Number: 318378-005US
3
333 MHz
FFFFh
189Ch
C4E0h
3138h
6270h
C4Eh
3
July 2009