HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 325

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
Table 100.
July 2009
Order Number: 318378-005US
De-allocate
DMA Engine
resources
Run time
management
of DMA
Engine
resources
Managing OS
driven plug
and play of
client
hardware
device
Managing OS
driven power
management
events to the
client Client
Hardware
and manage
system sleep
state
transitions
Task
Chipset Hardware
BIOS
DMA Engine
Device Software
Driver
I/O Device
Hardware
I/O Device
Software Driver
Other Restrictions,
Issues, Notes
Chipset Hardware
BIOS
DMA Engine
Device Software
Driver
I/O Device
Hardware
I/O Device
Software Driver
Other Restrictions,
Issues, Notes
Chipset Hardware
BIOS
DMA Engine
Device Software
Driver
I/O Device
Hardware
I/O Device
Software Driver
Other Restrictions,
Issues, Notes
Chipset Hardware
BIOS
DMA Engine
Device Software
Driver
I/O Device
Hardware
I/O Device
Software Driver
Other Restrictions,
Issues, Notes
Software Model Dependencies (Sheet 3 of 3)
Realm
®
5100 MCH Chipset
Note:
• None
• None
• Manages client request to free DMA Engine resources and programs DMA Engine
• None
• Client, via DMA Engine software driver, releases DMA Engine Resources
• As part of each Client Driver Unload, Reset, or Stop, DMA Engine resources must be
• Support inbound MMIO reads and writes.
• None
• Manages DMA Engine errors etc.
• Signals Client of DMA Engine errors
• None
• Makes necessary adjustments for any DMA Engine errors
• None
• Manages client request to free DMA Engine resources and programs DMA Engine
• Client must release DMA Engine resources during PnP events such as Stop, Surprise
• If DMA Engine driver is Unloaded or Stopped, Client Driver will be notified to De-
• Must be able to take device power state transition commands from OS and notify
• Must be able to drain DMA Engine traffic & release DMA Engine resources when
• Must indicate to software that it is now OK to report transition to D3 state
• Must be able to take device power state transition commands from OS and request
• Must be able to drain DMA Engine traffic in hardware if any & release DMA Engine
• Must indicate to OS software that it is now OK to report transition to D3 state
• If DMA Engine driver is powered Down or changed to low power state, Client Software
device registers to de-allocate resources
De-allocated
device registers to free indicated resources
removal, etc.
allocate DMA Engine resources.
client software to de-allocate DMA Engine resources
software issues the command to move to D3 state
Client Hardware to move to new (e.g., D3) state
resources when OS software issues command to move to D3 state
Drivers will be notified to De-allocate DMA Engine resources
Whether a STOP is treated the same as an UNLOAD (i.e., free all resources on
stop and reclaim them on start) is up to the Client Hardware/Software
combination.
Requirements
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
325