HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 8

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Intel
Datasheet
8
®
5100 Memory Controller Hub Chipset
3.12
3.11.2 PEXSTS: PCI Status Register .................................................................. 222
3.11.3 CCR: Class Code Register ...................................................................... 223
3.11.4 CB_BAR: DMA Engine Base Address Register ............................................ 223
3.11.5 CAPPTR: Capability Pointer Register ........................................................ 224
3.11.6 INTL: Interrupt Line Register.................................................................. 224
3.11.7 INTP: Interrupt Pin Register ................................................................... 224
3.11.8 DMACTRL: DMA Control Register............................................................. 224
3.11.9 Power Management Capability Structure .................................................. 226
3.11.10MSICAPID - Message Signaled Interrupt Capability ID Register ................... 227
3.11.11MSINXPTR - Message Signaled Interrupt Next Pointer Register.................... 228
3.11.12MSICTRL - Message Signaled Interrupt Control Register ............................. 228
3.11.13MSIAR: Message Signaled Interrupt Address Register ................................ 229
3.11.14MSIDR: Message Signaled Interrupt Data Register .................................... 230
3.11.15PEXCAPID: PCI Express* Capability ID Register ........................................ 231
3.11.16PEXNPTR: PCI Express* Next Pointer Register .......................................... 231
3.11.17PEXCAP - PCI Express* Capabilities Register............................................. 231
3.11.18PEXDEVCAP - Device Capabilities Register ................................................ 231
3.11.19PEXDEVCTRL - Device Control Register .................................................... 232
3.11.20PEXDEVSTS - PCI Express* Device Status Register.................................... 233
3.11.21DMA Error Logging ................................................................................ 234
3.11.22DMA Registers...................................................................................... 240
3.11.23DMA Channel Specific Registers .............................................................. 244
PCI Express* Per-Port Registers......................................................................... 251
3.11.9.1 PMCAP - Power Management Capabilities Register ....................... 226
3.11.9.2 PMCSR - Power Management Control and Status Register ............. 227
3.11.21.1CB_ERR_DOCMD - DMA Engine Error Do Command Register ......... 234
3.11.21.2FERR_CHANERR - First Error Channel Error Register .................... 235
3.11.21.3FERR_CHANCMD - First Error Channel Command Register............. 236
3.11.21.4FERR_CHANSTS - First Error Channel Status Register................... 237
3.11.21.5FERR_DESC_CTRL - First Error Descriptor Control Register ........... 237
3.11.21.6FERR_SADDR - First Error Source Address Register...................... 237
3.11.21.7FERR_DADDR - First Error Destination Address Register ............... 237
3.11.21.8FERR_TRANSFER_SIZE - First Error Transfer Size Register ............ 238
3.11.21.9FERR_NADDR - First Error Next Address Register......................... 238
3.11.21.10FERR_CHANCMP - First Error Channel Completion Address Register ...
3.11.21.11NERR_CHANERR - Next Channel Error Register .......................... 238
3.11.22.1CHANCNT - Channel Count ....................................................... 240
3.11.22.2XFERCAP - Transfer Capacity .................................................... 241
3.11.22.3INTRCTRL - Interrupt Control .................................................... 241
3.11.22.4ATTNSTATUS - Attention Status ................................................ 241
3.11.22.5CBVER - DMA Engine Version .................................................... 242
3.11.22.6PERPORT_OFFSET - Per-port Offset ........................................... 242
3.11.22.7INTRDELAY - Interrupt Delay Register ........................................ 243
3.11.22.8CS_STATUS: Chipset Status Register ......................................... 243
3.11.22.9CHAN_SYSERR_MSK[3:0]: Channel System Error Mask Register.... 243
3.11.23.1DMA_COMP[3:0]: DMA Compatibility Register ............................. 244
3.11.23.2CHANCTRL[3:0] - Channel Control Register ................................ 245
3.11.23.3CHANSTS[3:0]: Channel Status Register .................................... 245
3.11.23.4CHAINADDR[3:0] - Descriptor Chain Address Register.................. 246
3.11.23.5CHANCMD[3:0] - DMA Channel Command Register ...................... 247
3.11.23.6CHANCMP[3:0]: Channel Completion Address Register ................. 248
3.11.23.7CDAR[3:0]: Current Descriptor Address Register ......................... 248
3.11.23.8CHANERR[3:0] - Channel Error Register ..................................... 248
3.11.23.9CHANERRMSK[3:0]: Channel Error Mask Register ........................ 250
3.12.0.1 NXTPPRSET2 - Next Per Port Register Set ................................... 251
3.12.0.2 NXTPPRSET3 - Next Per Port Register Set ................................... 251
238
Intel
®
5100 MCH Chipset—Contents
Order Number: 318378-005US
July 2009