HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 221

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
July 2009
Order Number: 318378-005US
The PCI Command register follows a subset of the PCI Local Bus Specification, Rev. 2.3.
This register provides the basic control of the ability of the DMA Engine device to
initiate and respond to transactions sent to it and maintains compatibility with PCI
configuration space.
Device:
Function:
Offset:
10
9
8
7
6
5:4
3
2
1
0
Bit
RW
RO
RW
RV
RW
RV
RO
RW
RW
RO
Attr
®
5100 MCH Chipset
8
0
04h
0
0
0
0
0
00
0
0
0
0
Default
INTxDisable: Interrupt Disable
This bit controls the ability of the DMA Engine device to assert a legacy PCI
interrupt during DMA completions or DMA errors.
1: Legacy Interrupt mode is disabled
0: Legacy Interrupt mode is enabled
FB2B: Fast Back-to-Back Enable
This bit does not apply to the DMA Engine Device and hardwired to 0.
SERRE: SERR Message Enable
This bit indicates whether the DMA Engine device is allowed to signal a SERR
condition.
This field handles the reporting of fatal and non-fatal errors by enabling the error
pins ERR[2:0].
1: The DMA Engine device is enabled to send fatal/non-fatal errors.
0: The DMA Engine device is disabled from generating fatal/non-fatal errors.
Reserved
PERRRSP: Parity Error Response
Controls the response when a parity error is detected in the DMA Engine
1: The device can report Parity errors
0: Parity errors can be ignored by the device.
Reserved
SPCEN: Special Cycle Enable
This bit does not apply to the DMA Engine Device.
BME: Bus Master Enable
Controls the ability for the DMA Engine device to initiate transactions to memory
including MMIO
1: Enables the DMA Engine device to successfully complete memory read/write
requests.
0: Disables upstream memory writes/reads
If this bit is not set and the DMA Engine is programmed by software to process
descriptors, the chipset will flag read (write) errors (*DMA8/*DMA9) and also
record the errors in the CHANERR registers when it attempts to issue cache line
requests to memory.
MAEN: Memory Access Enable
Controls the ability for the DMA Engine Device to respond to memory mapped I/O
transactions initiated in the Intel
1: Allow MMIO accesses in the DMA Engine
0: Disable MMIO accesses in DMA Engine
This only applies to access CB_BAR space in Device 8, fn 1 where the MMIO space
resides (Requests from both fast/slow paths will be master-aborted)
IOAEN: I/O Access Enable
Controls the ability for the DMA Engine Device to respond to legacy I/O
transactions. The DMA Engine Device does not support/allow legacy I/O cycles.
®
5100 MCH Chipset in its range.
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
221